MT18VDDT12872PHG-262A1 datasheet, PDF

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MT18VDDT12872PHG-262A1: DescriptionDDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,; Categorystorage storage; File Size572KB，28 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT18VDDT12872PHG-262A1 Overview

DDR DRAM Module, 128MX72, 0.75ns, CMOS, PDMA200,

MT18VDDT12872PHG-262A1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	108914340
package instruction	DIMM, DIMM200,24
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	0.75 ns
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PDMA-N200
memory density	9663676416 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of terminals	200
word count	134217728 words
character code	128000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIMM
Encapsulate equivalent code	DIMM200,24
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum slew rate	3.645 mA
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	0.6 mm
Terminal location	DUAL

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1GB (x72, ECC, PLL)

200-PIN DDR SDRAM SODIMM

SMALL-OUTLINE

DDR SDRAM DIMM

Features

• 200-pin, small-outline, dual in-line memory

module (SODIMM)

• Supports ECC error detection and correction

• Fast data transfer rate: PC2100 and PC2700

• Utilizes 267 MT/s and 333 MT/s DDR SDRAM

components

• 1GB (128 Meg x 72, stacked)

• V

= V

Q = +2.5V

• V

DDSPD

= +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/re-

ceived with data—i.e., source-synchronous data

capture

• Differential clock inputs CK and CK#

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 7.8125µs maximum average periodic refresh

interval

• Serial Presence Detect (SPD) with EEPROM

• Programmable READ CAS latency

• Gold edge contacts

MT18VDDT12872PH(I) – 1GB

For the lastest data sheet, please refer to the Micron



Web site:

www.micron.com/module.

Figure 1: 200-Pin SODIMM (MO-224)

Height 1.25in. (31.75mm)

OPTIONS

MARKING

• Operating Temperature Range

Commercial (0°C

≤

+70°C)

Industrial (-40°C

≤

+85°C)

• Package

200-pin SODIMM (standard)

200-pin SODIMM (lead-free)

• Clock Frequency/CAS Latency

167 MHz (333 MT/s) CL = 2.5

133 MHz (266 MT/s) CL = 2

133 MHz (266 MT/s) CL = 2.5

• PCB Height

Standard 1.25in. (31.75mm)

NOTE:

None

-335

-262

-26A

-265

1. CL = Device CAS (READ) Latency.

2. Consult Micron for product availability.

Table 1:

Address Table

1GB

8K (A0–A12)

4 (BA0, BA1)

512Mb (64 Meg x 8)

2K (A0–A9, A11)

2 (S0#, S1#)

Refresh Count

Row Addressing

Device Bank Addressing

Base Device Configuration

Column Addressing

Module Rank Addressing

pdf: 09005aef81697898/source: 09005aef8169786e

DD18C128x72PHG.fm - Rev. A 10/04 EN

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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