PCA9512AD-T datasheet, PDF - EEWORLD Datasheet

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PCA9512AD-T: DescriptionBuffers and line drivers levshift i2c/SMbus bus buffer; Categorysemiconductor logic; File Size145KB，23 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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PCA9512AD-T Overview

Buffers and line drivers levshift i2c/SMbus bus buffer

PCA9512AD-T Parametric

Parameter Name	Attribute value
Maker	NXP
Product Category	Buffers and Line Drivers
RoHS	yes
Maximum operating temperature	+ 85 C
Minimum operating temperature	- 40 C
Installation style	SMD/SMT
Package/box	SO
Encapsulation	Reel

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PCA9512A

Level shifting hot swappable I

C-bus and SMBus bus buffer

Rev. 04 — 19 August 2009

Product data sheet

1. General description

The PCA9512A is a hot swappable I

C-bus and SMBus buffer that allows I/O card

insertion into a live backplane without corruption of the data and clock buses and includes

two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems

while maintaining the best noise margin for each voltage level. Either pin may be powered

with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply

voltage is higher. Control circuitry prevents the backplane from being connected to the

card until a stop bit or bus idle occurs on the backplane without bus contention on the

card. When the connection is made, the PCA9512A provides bidirectional buffering,

keeping the backplane and card capacitances isolated.

The PCA9512A rise time accelerator circuitry allows the use of weaker DC pull-up

currents while still meeting rise time requirements. The PCA9512A incorporates a digital

input pin that enables and disables the rise time accelerators on all four SDAn and SCLn

pins.

During insertion, the PCA9512A SDAn and SCLn pins are precharged to 1 V to minimize

the current required to charge the parasitic capacitance of the chip.

The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to

be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and

to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A

cannot

connect to the

static offset I/Os used on the PCA9515/15A/16/16A/18, PCA9517 B side, or

P82B96 Sx/y side.

2. Features

Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and

SCL corruption during live board insertion and removal from multipoint backplane

systems

Compatible with I

C-bus Standard mode, I

C-bus Fast mode, and SMBus standards

Built-in

∆V/∆t

rise time accelerators on all SDA and SCL lines (0.6 V threshold) with

ability to disable

∆V/∆t

rise time accelerator through the ACC pin for lightly loaded

systems, requires the bus pull-up voltage and respective supply voltage (V

or V

CC2

)

to be the same

5 V to 3.3 V level translation with optimum noise margin

High-impedance SDAn and SCLn pins for V

or V

CC2

= 0 V

1 V precharge on all SDAn and SCLn pins

Supports clock stretching and multiple master arbitration and synchronization

Operating power supply voltage range: 2.7 V to 5.5 V

0 Hz to 400 kHz clock frequency

NXP Semiconductors

PCA9512A

Level shifting hot swappable I

C-bus and SMBus bus buffer

STOP condition is seen on the SDAIN and SCLIN pins, the connect circuitry is activated,

connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V precharge circuitry is

disabled when the connection is made, unless the ACC pin is LOW; the rise time

accelerators are enabled at this time also.

8.2 Connect circuitry

Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as

SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that

isolates the input bus capacitance from the output bus capacitance while communicating.

If V

≠

CC2

, then a level shifting function is performed between input and output. A LOW

forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the

PCA9512A. The same is also true for the SCLn pins. Noise between 0.7V

and V

the SDAIN and SCLIN pins, and 0.7V

CC2

and V

CC2

on the SDAOUT and SCLOUT pins is

generally ignored because a falling edge is only recognized when it falls below 0.7V

for

SDAIN and SCLIN (or 0.7V

CC2

for SDAOUT and SCLOUT pins) with a slew rate of at least

1.25 V/µs. When a falling edge is seen on one pin, the other pin in the pair turns on a

pull-down driver that is referenced to a small voltage above the falling pin. The driver will

pull the pin down at a slew rate determined by the driver and the load. The ﬁrst falling pin

may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial

pull-down rate will continue until it is LOW. If the ﬁrst falling pin has a slow slew rate, then

the second pin will be pulled down at its initial slew rate only until it is just above the ﬁrst

pin voltage then they will both continue down at the slew rate of the ﬁrst.

Once both sides are LOW they will remain LOW until all the external drivers have stopped

driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value

by external drivers, which is the case for clock stretching and is typically the case for

acknowledge, and one side external driver stops driving, that pin will rise and rise above

the nominal offset voltage until the internal driver catches up and pulls it back down to the

offset voltage. This bounce is worst for low capacitances and low resistances, and may

become excessive. When the last external driver stops driving a LOW, that pin will bounce

up and settle out just above the other pin as both rise together with a slew rate determined

by the internal slew rate control and the RC time constant. As long as the slew rate is at

least 1.25 V/µs, when the pin voltage exceeds 0.6 V, the rise time accelerator circuits are

turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time

accelerator circuits will be disabled, but the pull-down driver will still turn off.

8.3 Maximum number of devices in series

Each buffer adds about 0.1 V dynamic level offset at 25

°C

with the offset larger at higher

temperatures. Maximum offset (V

offset

) is 0.150 V with a 10 kΩ pull-up resistor. The LOW

level at the signal origination end (master) is dependent upon the load and the only

speciﬁcation point is the I

C-bus speciﬁcation of 3 mA will produce V

< 0.4 V, although if

lightly loaded the V

may be ~0.1 V. Assuming V

= 0.1 V and V

offset

= 0.1 V, the level

after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the

rising edge accelerator (about 0.6 V). With great care a system with four buffers may

work, but as the V

moves up from 0.1 V, noise or bounces on the line will result in ﬁring

the rising edge accelerator thus introducing false clock edges. Generally it is

recommended to limit the number of buffers in series to two, and to keep the load light to

minimize the offset.

PCA9512A_4

Product data sheet

Rev. 04 — 19 August 2009

5 of 23

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