INTEGRATED CIRCUITS
PCA9561
Quad 6-bit multiplexed
I
2
C EEPROM DIP switch
Product data sheet
Supersedes data of 2003 Jun 27
2004 May 17
Philips
Semiconductors
Philips Semiconductors
Product data sheet
Quad 6-bit multiplexed I
2
C EEPROM DIP switch
PCA9561
FEATURES
via I
2
C-bus
•
Selection of non-volatile register_n as source to MUX_OUT pins
•
I
2
C-bus can override MUX_SELECT pin in selecting output
source
The PCA9561 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption. The main advantage of the PCA9561 over
older devices, such as the PCA9559 or PCA9560, is that it contains
four internal non-volatile EEPROM registers instead of just one or
two, allowing five independent settings which allows a more
accurate CPU voltage tuning depending on specific applications.
The PCA9561 has 2 address pins, allowing up to 4 devices to be
placed on the same I
2
C-bus or SMBus.
•
6-bit 5-to-1 multiplexer DIP switch
•
4 internal non-volatile registers
•
Internal non-volatile registers programmable and readable via
I
2
C-bus
PIN CONFIGURATION
SCL
SDA
A0
MUX_IN_A
MUX_IN_B
MUX_IN_C
MUX_IN_D
MUX_IN_E
MUX_IN_F
1
2
3
4
5
6
7
8
9
20 V
DD
19 WP
18 A1
17 MUX_OUT_A
16 MUX_OUT_B
15 MUX_OUT_C
14 MUX_OUT_D
13 MUX_OUT_E
12 MUX_OUT_F
11 MUX_SELECT
•
6 open drain multiplexed outputs
•
400 kHz maximum clock frequency
•
Operating supply voltage 3.0 V to 3.6 V
•
5 V and 2.5 V tolerant inputs/outputs
•
Useful for Speed Step® configuration of laptop
•
2 address pins, allowing up to 4 devices on the I
2
C-bus
•
MUX_IN values readable via I
2
C-bus
•
ESD protection exceeds 200 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
GND 10
SW00823
PIN DESCRIPTION
PIN
1
2
3
4–9
10
11
12–17
18
19
20
SYMBOL
I
2
C SCL
I
2
C SDA
A0
MUX_IN_A–F
GND
MUX_SELECT
MUX_OUT_F–A
A1
WP
V
DD
FUNCTION
Serial I
2
C-bus clock
Serial bi-directional I
2
C-bus data
A0 address
External inputs to multiplexer
Ground
Selects MUX_IN inputs or register
contents for MUX_OUT outputs
Open drain multiplexed outputs
A1 address
Non-volatile register write-protect
Power supply: +3.0 to +3.6 V
•
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA.
DESCRIPTION
The PCA9561 is a 20-pin CMOS device consisting of four 6-bit
non-volatile EEPROM registers, 6 hardware pin inputs and a 6-bit
multiplexed output. It is used for DIP switch-free or jumper-less
system configuration and supports Mobile and Desktop VID
Configuration, where 5 preset values (4 sets of internal non-volatile
registers and 1 set of external hardware pins) set processor voltage
for operation in various performance or battery conservation sleep
modes. The PCA9561 is also useful in server and
telecom/networking applications when used to replace DIP switches
or jumpers, since the settings can be easily changed via I
2
C/SMBus
without having to power down the equipment to open the cabinet.
The non-volatile memory retains the most current setting selected
before the power is turned off.
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SO
20-Pin Plastic TSSOP
TEMPERATURE RANGE
–40 to +85
°C
–40 to +85
°C
ORDER CODE
PCA9561D
PCA9561PW
TOPSIDE MARK
PCA9561D
PCA9561
DRAWING NUMBER
SOT163-1
SOT360-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
®
Speed Step is a registered trademark of Intel Corp.
2004 May 17
2
Philips Semiconductors
Product data sheet
Quad 6-bit multiplexed I
2
C EEPROM DIP switch
PCA9561
BLOCK DIAGRAM
PCA9561
WRITE PROTECT
NON-VOLATILE
REGISTER 0
6-BIT EEPROM
6
6-BIT
4 TO 1
DEMULTIPLEXER
NON-VOLATILE
REGISTER 1
6-BIT EEPROM
6
NON-VOLATILE
REGISTER 2
6-BIT EEPROM
6
NON-VOLATILE
REGISTER 3
6-BIT EEPROM
8
6
A0
A1
SCL
SDA
INPUT
FILTER
2
I C LOGIC
2
6
V
DD
POWER-ON
RESET
MUX_OUT_A
GND
4
6-BIT
2 TO 1
DEMULTIPLEXER
MUX_OUT_B
MUX_IN_A
MUX_OUT_C
MUX_IN_B
MUX_OUT_D
MUX_IN_C
MUX_OUT_E
MUX_OUT_F
MUX_IN_D
6
MUX_IN_E
MUX_IN_F
MUX_SELECT
SELECT LOGIC
SW00842
2004 May 17
3
Philips Semiconductors
Product data sheet
Quad 6-bit multiplexed I
2
C EEPROM DIP switch
PCA9561
DEVICE ADDRESS
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9561 is
shown in Figure 1. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The last bit of the slave address byte defines the operation to be
performed. When set to logic 1 a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9561, which will be stored
in the control register. This register can be written and read via the
I
2
C-bus.
D7
MSB
1
0
0
1
1
A1
A0
LSB
R/W
D6
D5
D4
D3
D2
D1
D0
SW00954
Figure 2. Control Register
FIXED
PROGRAMMABLE
SW00955
Figure 1. Slave address
CONTROL REGISTER DEFINITION
Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is
reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged.
Table 1. Register Addresses
D7
0
0
0
0
1
D6
0
0
0
0
1
D5
0
0
0
0
1
D4
0
0
0
0
1
D3
0
0
0
0
1
D2
0
0
0
0
1
D1
0
0
1
1
1
D0
0
1
0
1
1
REGISTER
NAME
EEPROM 0
EEPROM 1
EEPROM 2
EEPROM 3
MUX_IN
TYPE
Read/Write
Read/Write
Read/Write
Read/Write
Read
REGISTER
FUNCTION
EEPROM byte 0
register
EEPROM byte 1
register
EEPROM byte 2
register
EEPROM byte 3
register
MUX_IN values
register
Table 2. Commands
D7
1
1
1
1
1
1
D6
1
1
1
1
1
1
D5
1
1
1
1
1
1
D4
1
1
1
1
1
1
D3
1
1
1
1
1
1
D2
0
1
0
1
X
X
D1
0
0
X
X
1
X
D0
0
0
1
1
0
1
COMMAND
MUX_OUT from EEPROM byte 0
MUX_OUT from EEPROM byte 1
MUX_OUT from EEPROM byte 2
MUX_OUT from EEPROM byte 3
MUX_OUT from MUX_IN
MUX_OUT from MUX_SELECT
2
NOTE:
1. All other combinations are reserved.
2. MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT.
2004 May 17
4
Philips Semiconductors
Product data sheet
Quad 6-bit multiplexed I
2
C EEPROM DIP switch
PCA9561
REGISTER DESCRIPTION
If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP
condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the
following STOP condition. Up to four bytes can be sent sequentially. If any more data bytes are sent after the second byte, they will not be
acknowledged and no bytes will be written to the non-volatile registers. After a byte is read from or written to the EEPROM, the part
automatically points to the next non-volatile register. If the command code was FFH, the MUX_IN values are sent with the three MSBs padded
with zeroes as shown below. If the command codes was 00H, then the non-volatile register 1 is sent, and if the command code was 01H, then
the non-volatile register 1 is sent.
EEPROM Byte 0 Register
D7
Write
Read
Default
X
0
0
D6
X
0
0
D5
EEPROM 0
Data F
EEPROM 0
Data F
0
D4
EEPROM 0
Data E
EEPROM 0
Data E
0
D3
EEPROM 0
Data D
EEPROM 0
Data D
0
D2
EEPROM 0
Data C
EEPROM 0
Data C
0
D1
EEPROM 0
Data B
EEPROM 0
Data B
0
D0
EEPROM 0
Data A
EEPROM 0
Data A
0
EEPROM Byte 1 Register
D7
Write
Read
Default
X
0
0
D6
X
0
0
D5
EEPROM 1
Data F
EEPROM 1
Data F
0
D4
EEPROM 1
Data E
EEPROM 1
Data E
0
D3
EEPROM 1
Data D
EEPROM 1
Data D
0
D2
EEPROM 1
Data C
EEPROM 1
Data C
0
D1
EEPROM 1
Data B
EEPROM 1
Data B
0
D0
EEPROM 1
Data A
EEPROM 1
Data A
0
EEPROM Byte 2 Register
D7
Write
Read
Default
X
0
0
D6
X
0
0
D5
EEPROM 2
Data F
EEPROM 2
Data F
0
D4
EEPROM 2
Data E
EEPROM 2
Data E
0
D3
EEPROM 2
Data D
EEPROM 2
Data D
0
D2
EEPROM 2
Data C
EEPROM 2
Data C
0
D1
EEPROM 2
Data B
EEPROM 2
Data B
0
D0
EEPROM 2
Data A
EEPROM 2
Data A
0
EEPROM Byte 3 Register
D7
Write
Read
Default
X
0
0
D6
X
0
0
D5
EEPROM 3
Data F
EEPROM 3
Data F
0
D4
EEPROM 3
Data E
EEPROM 3
Data E
0
D3
EEPROM 3
Data D
EEPROM 3
Data D
0
D2
EEPROM 3
Data C
EEPROM 3
Data C
0
D1
EEPROM 3
Data B
EEPROM 3
Data B
0
D0
EEPROM 3
Data A
EEPROM 3
Data A
0
MUX_IN Register
D7
Read
0
D6
0
D5
MUX_IN
Data F
D4
MUX_IN
Data E
D3
MUX_IN
Data D
D2
MUX_IN
Data C
D1
MUX_IN
Data B
D0
MUX_IN
Data A
If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the
read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code.
The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s.
The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The
data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the
non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins.
After a valid I
2
C write operation to the EEPROM, the part cannot be addressed via the I
2
C for 3.6 ms. If the part is addressed prior to this time,
the part will not acknowledge its address.
NOTE:
1. To ensure data integrity, the non-volatile register must be internally write protected when V
DD
to the I
2
C-bus is powered down or V
DD
to the
component is dropped below normal operating levels.
2004 May 17
5
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