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74ALVC16841MTD_Q

Description
Bus transceiver 20-bit transparent L
Categorysemiconductor    Other integrated circuit (IC)   
File Size94KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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74ALVC16841MTD_Q Overview

Bus transceiver 20-bit transparent L

74ALVC16841MTD_Q Parametric

Parameter NameAttribute value
MakerFairchild
RoHSno
logical typeTransparent Latch
logic series74AL
Maximum operating temperature85 C
Minimum operating temperature- 40 C
Package/boxTSSOP-56
EncapsulationTube
Installation styleSMD/SMT
Number of circuits20
74ALVC16841 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
November 2001
Revised November 2001
74ALVC16841
Low Voltage 20-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74ALVC16841 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16841 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.65V–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(D
n
to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
3.9 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion and withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC16841MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
LE
n
D
0
–D
19
O
0
–O
19
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation
DS500690
www.fairchildsemi.com

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74ALVC16841MTD_Q
Description Bus transceiver 20-bit transparent L
Maker Fairchild
RoHS no
logical type Transparent Latch
logic series 74AL
Maximum operating temperature 85 C
Minimum operating temperature - 40 C
Package/box TSSOP-56
Encapsulation Tube
Installation style SMD/SMT
Number of circuits 20
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