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A3PN030-Z1VQG100

Description
fpga - field programmable gate array 30k system gates proasic3 nano
CategoryProgrammable logic devices    Programmable logic   
File Size4MB,106 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Environmental Compliance
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A3PN030-Z1VQG100 Overview

fpga - field programmable gate array 30k system gates proasic3 nano

A3PN030-Z1VQG100 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerActel
package instruction14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
Reach Compliance Codecompliant
JESD-30 codeS-PQFP-G100
JESD-609 codee3
length14 mm
Humidity sensitivity level3
Configurable number of logic blocks768
Equivalent number of gates30000
Number of entries77
Number of logical units768
Output times77
Number of terminals100
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
organize768 CLBS, 30000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeTFQFP
Encapsulate equivalent codeTQFP100,.63SQ
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply1.5,1.5/3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width14 mm
Revision 8
ProASIC3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
®
Advanced I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
Low Power
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18 organization)
Low Power ProASIC 3 nano Products
1.5 V Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
®
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Enhanced Commercial Temperature Range
• –20°C to +70°C
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
ProASIC3 nano-Z Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
2
4,608-Bit Blocks
2
FlashROM Kbits
Secure (AES) ISP
2
Integrated PLL in CCCs
2
VersaNet Globals
I/O Banks
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
Package Pins
QFN
VQFP
10,000
86
260
1
4
2
34
34
QN48
15,000
128
384
1
4
3
49
QN68
20,000
172
520
1
4
3
49
52
QN68
A3PN010
A3PN015
A3PN020
A3PN030Z
1
30,000
256
768
1
6
2
77
83
QN48, QN68
VQ100
A3PN060
A3PN125
A3PN250
A3N250Z
250,000
2,048
6,144
36
8
1
Yes
1
18
4
68
68
A3PN060Z A3PN125Z
60,000
512
1,536
18
4
1
Yes
1
18
2
71
71
125,000
1,024
3,072
36
8
1
Yes
1
18
2
71
71
VQ100
VQ100
VQ100
Notes:
1. A3PN030 is available in the Z feature grade only.
2. A3PN030 and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the
ProASIC3
and
ProASIC3E
datasheets.
† A3PN030 and smaller devices do not support this feature.
April 2010
© 2010 Actel Corporation
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