Integrated
Circuit
Systems, Inc.
ICS950401
AMD - K8™ System Clock Chip
Recommended Application:
AMD K8 Systems
Pin Configuration
*FS0/REF0 1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS1*
GND
VDDREF
REF2/FS2*
SPREAD*
VDDA
GNDA
CPUCLKT0
CPUCLKC0
GND
VDDCPU
CPUCLKT1
CPUCLKC1
VDD
GND
GNDA
VDDA
48MHz
GND
VDD
24_48MHz/Sel24_48#*
GND
SDATA
SCLK
Output Features:
VDDREF 2
•
2 - Differential pair push-pull CPU clocks @ 3.3V
X1 3
•
7 - PCI (Including 1 free running) @3.3V
X2 4
•
3 - Selectable HT/PCI 66/33MHz @3.3V
GND 5
•
1 - 48MHz, @3.3V fixed.
*PCI33/HT66SEL# 6
•
1 - 24/48MHz @ 3.3V
PCICLK33/HT66_0 7
•
3 - REF @3.3V, 14.318MHz.
PCICLK33/HT66_1 8
Features:
VDDPCI 9
•
Up to 220MHz frequency support
GND 10
•
Support power management: PCI stop and stop
PCICLK33/HT66_2 11
2
clocks controlled by I C.
NC 12
•
Spread spectrum for EMI reduction
PCICLK0 13
•
Uses external 14.318MHz crystal
PCICLK1 14
2
•
I C programmability features
GND 15
VDDPCI 16
•
Supports Hypes transport technology (HT66 output).
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK_F
*PCI_STOP#
17
18
19
20
21
22
23
24
48-SSOP/ TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS2 FS1 FS0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
PCI33_HT66
SEL#
X
0
1
X
X
X
X
X
X
CPU
Hi-Z
X
X
180.00
220.00
100.00
133.33
166.66
200.00
PCI33
Hi-Z
X/6
X/6
30.00
36.56
33.33
33.33
33.33
33.33
PCI33_HT66
Hi-Z
X/3
X/6
60.00
73.12
33.33/66.66
33.33/66.66
33.33/66.66
33.33/66.66
COMMENTS
Tri-State Mode
Bypass Mode
Bypass Mode
10% under-clk
10% over-clk
Athlon Compatible
Athlon Compatible
Reserved
Hammer Operation
REF (2:0)
CPU
DIVDER
Stop
CPUCLKC (1:0)
CPUCLKT (1:0)
SDATA
SCLK
FS (2:0)
PCI33/HT66SEL#
PCI_STOP#
SPREAD
24_48SEL#
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
PCICLK (5:0)
PCICLK_F
X2
PCICLK33/HT66(2:0)
0499C—11/01/04
ICS950401
ICS950401
Pin Descriptions
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PIN
NAME
*FS0/REF0
VDDREF
X1
X2
GND
*PCI33/HT66SEL#
PCICLK33/HT66_0
PCICLK33/HT66_1
VDDPCI
GND
PCICLK33/HT66_2
NC
PCICLK0
PCICLK1
GND
VDDPCI
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK_F
*PCI_STOP#
SCLK
SDATA
GND
24_48MHz/Sel24_48#*
VDD
GND
48MHz
VDDA
GNDA
GND
VDD
CPUCLKC1
CPUCLKT1
VDDCPU
GND
CPUCLKC0
CPUCLKT0
GNDA
VDDA
SPREAD*
REF2/FS2*
VDDREF
GND
REF1/FS1*
PIN
TYPE
I/O
PWR
IN
OUT
PWR
IN
IN
IN
PWR
PWR
IN
NC
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
I/O
I/O
IN
I/O
PWR
I/O
PWR
PWR
OUT
PWR
PWR
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
IN
I/O
PWR
PWR
I/O
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz,
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
No Connect
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
Input select pin, Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ground pin.
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
Power supply, nominal 3.3V
Ground pin.
48MHz clock output.
3.3V power for the PLL core.
Ground pin for the PLL core.
Ground pin.
Power supply, nominal 3.3V
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
True clock of differential CPU outputs. Push-pull requires external termination.
Supply for CPU clocks, 3.3V nominal
Ground pin.
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
True clock of differential CPU outputs. Push-pull requires external termination.
Ground pin for the PLL core.
3.3V power for the PLL core.
Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable
spread spectrum functionality.
14.318 MHz reference clock / Frequency select latch input pin.
Ref, XTAL power supply, nominal 3.3V
Ground pin.
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
0499C—11/01/04
2
ICS950401
General Description
The
ICS950401
is a main clock synthesizer chip for AMD-K8. This provides all clocks required for Clawhammer and
Sledgehammer systems.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS950401
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDA = PLL2
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
Pin 32
Pin 43
Pin 2
Skew Characteristics
Parameter
T
sk_CPU_CPU
T
sk_CPU_PCI
T
sk_PCI_PCI
T
sk_PCI33-HT66
T
sk_CPU_HT66
T
sk_CPU_HT66
T
sk_CPU_CPU
T
sk_CPU_PCI
T
sk_PCI_PCI
T
sk_PCI33-HT66
T
sk_CPU_HT66
T
sk_CPU_HT66
time variant skew
varies over
V, T changes
time independent
skew
not dependent on
V, T changes
Description
Test Conditons
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured at x-ing of CPU,
1.5V of PCI clock
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured at x-ing of CPU,
1.5V of PCI clock
Skew
Window
250
2000
500
500
2000
500
200
200
200
200
200
200
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
0499C—11/01/04
3
ICS950401
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
0499C—11/01/04
Not acknowledge
stoP bit
4
ICS950401
Byte0: Functionality and Frequency Select
Bit
Pin #
PWD
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
45
48
1
Description
Write disable (Write once)
1
Spread Spectrum Enable. 0 =
Disable; 1 = Enable
2
Reserved
Reserved
FS2
FS1
FS0
Write Enable
3
Notes:
1.
Write Disable. A '1' written to this bit after a '1' is written to BYTE0/bit 0 will permanently disable writing to I2C until
the part is powered off. Once the clock generator has been write disabled, the SMBus controller should still accept and
acknowledge subsequent write cycles but it should not modify any of the registers.
2.
Spread Pin SS Bit Spread Enable
0
0
1
1
0
1
0
1
Disabled
Enabled
Enabled
Enabled
3.
A '1' written to this bit after power-up will enable writing to I2C. Subsequent '0's written to this bit will disable
modification of all registers except this single bit. When a '1' is written to Byte 0 Bit 7, all modification is permanently
disabled until the device power cycles. Block write transactions to the interface will complete, however unless the
interface has been previously unlocked, the writes will have no effect. The effect of writing to this bit does not take effect
until the subsequent block write command.
4. Clarification on frequency select on power-up:
i. Upon power-up, Byte0, bits (5:1) [FS(4:0)] are set to default hardware settings.
ii. A '1' is written to Byte0, bit 0 to enable software control.
iii. Every time Byte0 is written, frequency input defaults will be affected.
iv. If a '0' is written to Byte0, bit0, the software control is disabled. Disabling software control does not cause the
contents of Byte0
to default back to hardware setting for FS(4:0).
0499C—11/01/04
5
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