IMPORTANT NOTICE
Dear customer,
As from August 2
nd
2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
Company name - NXP B.V.
is replaced with
ST-NXP Wireless.
Copyright
- the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site
-
http://www.nxp.com
is replaced with
http://www.stnwireless.com
Contact information
- the list of sales offices previously obtained by sending
an email to
salesaddresses@nxp.com
, is now found at
http://www.stnwireless.com
under Contacts.
●
●
●
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
www.stnwireless.com
ISP1506A; ISP1506B
ULPI Hi-Speed USB OTG transceiver
Rev. 02 — 28 August 2008
Product data sheet
1. General description
The ISP1506 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully
compliant with
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”, Ref. 2 “On-The-Go
Supplement to the USB 2.0 Specification Rev. 1.3”
and
Ref. 3 “UTMI+ Low Pin Interface
(ULPI) Specification Rev. 1.1”.
The ISP1506 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through an 8-pin interface.
The ISP1506 can interface to devices with digital I/O voltages in the range of 1.65 V to
1.95 V.
The ISP1506 is available in HVQFN24 package.
2. Features
I
Fully complies with:
N
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
N
Ref. 2 “On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3”
N
Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1”
I
Interfaces to host, peripheral and OTG device cores; optimized for portable devices or
system ASICs with built-in USB OTG device core
I
Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N
Integrated 45
Ω ±
10 % high-speed termination resistors, 1.5 kΩ
±
5 % full-speed
device pull-up resistor, and 15 kΩ
±
5 % host termination resistors
N
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N
USB clock and data recovery to receive USB data up to
±500
ppm
N
Insertion of stuff bits during transmit and discarding of stuff bits during receive
N
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I
Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
I
I
I
I
I
N
Integrated 5 V charge pump; also supports external charge pump or 5 V V
BUS
switch
N
Complete control over bus resistors
N
Data line and V
BUS
pulsing session request methods
N
Integrated V
BUS
voltage comparators
N
Integrated cable (ID) detector
Highly optimized ULPI compliant
N
60 MHz, 8-bit interface between the core and the transceiver
N
Supports 4-bit dual-edge data bus
N
Supports 60 MHz output clock configuration
N
Integrated Phase-Locked Loop (PLL), supporting one crystal or clock frequency:
19.2 MHz (ISP1506ABS) and 26 MHz (ISP1506BBS)
N
Fully programmable ULPI-compliant register set
N
Internal Power-On Reset (POR) circuit
Flexible system integration and very low current consumption, optimized for portable
devices
N
Power-supply input range is 3.0 V to 3.6 V
N
Internal voltage regulator supplies 3.3 V and 1.8 V
N
Charge pump regulator outputs 4.75 V to 5.25 V at a current of up to 50 mA,
tunable using an external capacitor
N
Supports interfacing I/O voltage of 1.65 V to 1.95 V; separate I/O voltage pins
minimize crosstalk
N
Typical operating current of 10 mA to 48 mA, depending on the USB speed and
bus utilization; not including the charge pump
N
Typical suspend current of 35
µA
Full industrial grade operating temperature range from
−40 °C
to +85
°C
4 kV ElectroStatic Discharge (ESD) protection at pins DP, DM, ID, V
BUS
and GND
Available in a small HVQFN24 (4 mm
×
4 mm) Restriction of Hazardous Substances
(RoHS) compliant, halogen-free and lead-free package
3. Applications
I
I
I
I
Digital still camera
Digital TV
Digital Video Disc (DVD) recorder
External storage device, for example:
N
Magneto-Optical (MO) drive
N
Optical drive: CD-ROM, CD-RW, DVD
N
Zip drive
Mobile phone
MP3 player
PDA
Portable Media Player (PMP)
Printer
Scanner
© NXP B.V. 2008. All rights reserved.
I
I
I
I
I
I
ISP1506A_ISP1506B_2
Product data sheet
Rev. 02 — 28 August 2008
2 of 79
NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
I
Set-Top Box (STB)
I
Video camera
4. Ordering information
Table 1.
Part
Type number
Marking
Crystal or
clock
frequency
19.2 MHz
26 MHz
Ordering information
Package
Name
Description
Version
ISP1506ABS
ISP1506BBS
06A
[1]
06B
[1]
HVQFN24
HVQFN24
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
×
4
×
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
×
4
×
0.85 mm
SOT616-1
SOT616-1
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1506A_ISP1506B_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 28 August 2008
3 of 79
NXP Semiconductors
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
5. Block diagram
CLOCK
STP
ULPI
INTERFACE
DIR
NXT
4
19
17
16
18
20, 22,
23, 24
ULPI
INTERFACE
CONTROLLER
TERMINATION
RESISTORS
USB DATA
SERIALIZER
4
HS USB ATX
DP
USB DATA
DESERIALIZER
V
BUS
valid external
3
DM
DATA[3:0]
REGISTER
MAP
USB
CABLE
OTG MODULE
ID
DETECTOR
5
ID
DRV V
BUS
DRV V
BUS
external
RESET_N/
PSW_N
14
POWER-ON
RESET
global
reset
V
BUS
COMPARATORS
10
SRP CHARGE
AND DISCHARGE
RESISTORS
V
BUS
/
FAULT
PLL
global
clocks
XTAL1
XTAL2
V
CC(I/O)
REG3V3
REG1V8
V
CC
12
13
1, 21
CRYSTAL
OSCILLATOR
5 V CHARGE
PUMP SUPPLY
8
7
6
C_A
C_B
CPGND
interface voltage
internal power
ISP1506
11
15
9
VOLTAGE
REGULATOR
V
REF
BAND GAP
REFERENCE
VOLTAGE
2
RREF
004aaa598
Fig 1.
Block diagram
ISP1506A_ISP1506B_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 28 August 2008
4 of 79
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