ZXMC3A17DN8
COMPLEMENTARY 30V ENHANCEMENT MODE MOSFET
SUMMARY
N-Channel : V
(BR)DSS
= 30V : R
DS(on)
= 0.050 ; I
D
= 5.4A
P-Channel : V
(BR)DSS
= -30V : R
DS(on)
= 0.070 ; I
D
= -4.4A
DESCRIPTION
This new generation of trench MOSFETs from Zetex utilizes a unique structure that
combines the benefits of low on-resistance with fast switching speed. This makes
them ideal for high efficiency, low voltage, power management applications.
SO8
FEATURES
•
Low on-resistance
•
Fast switching speed
•
Low threshold
•
Low gate drive
•
Low profile SOIC package
APPLICATIONS
•
Motor drive
•
LCD backlighting
Q1 = N-channel
Q2 = P-channel
ORDERING INFORMATION
DEVICE
ZXMC3A17DN8TA
ZXMC3A17DN8TC
REEL SIZE
7”
13”
TAPE WIDTH
12mm
12mm
QUANTITY PER REEL
500 units
2500 units
PINOUT
DEVICE MARKING
•
ZXMC
3A17
Top View
ISSUE 1 - OCTOBER 2005
1
SEMICONDUCTORS
ZXMC3A17DN8
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
(V
GS
= 10V; T
A
=25°C)
(b)(d)
(V
GS
= 10V; T
A
=70°C)
(b)(d)
(V
GS
= 10V; T
A
=25°C)
(a)(d)
Pulsed Drain Current
(c)
Continuous Source Current (Body Diode)
(b)
Pulsed Source Current (Body Diode)
(c)
Power Dissipation at T
A
=25°C
(a) (d)
Linear Derating Factor
Power Dissipation at T
A
=25°C
(a) (e)
Linear Derating Factor
Power Dissipation at T
A
=25°C
(b) (d)
Linear Derating Factor
Operating and Storage Temperature Range
P
D
P
D
T
j
, T
stg
SYMBOL
V
DSS
V
GS
I
D
ADVANCE INFORMATION
N-channel
30
±20
5.4
4.3
4.1
23
2.6
23
1.25
10
1.8
14
2.1
17
P-channel
-30
±20
-4.4
-3.6
-3.4
-20
-2.5
-20
UNIT
V
V
A
I
DM
I
S
I
SM
P
D
A
A
A
W
mW/°C
W
mW/°C
W
mW/°C
°C
-55 to +150
THERMAL RESISTANCE
PARAMETER
Junction to Ambient
(a) (d)
Junction to Ambient
(a) (e)
Junction to Ambient
(b) (d)
SYMBOL
R
JA
R
JA
R
JA
VALUE
100
70
60
UNIT
°C/W
°C/W
°C/W
NOTES:
(a) For a dual device surface mounted on 25mm x 25mm FR4 PCB with high coverage of single sided 1oz copper, in still air conditions.
(b) For a dual device surface mounted on FR4 PCB measured at t 10 sec.
(c) Repetitive rating 25mm x 25mm FR4 PCB, D = 0.02, pulse width = 300 s - pulse width limited by maximum junction temperature.
(d) For a dual device with one active die.
(e) For dual device with two active die running at equal power.
ISSUE 1 - OCTOBER 2005
SEMICONDUCTORS
2
ADVANCE INFORMATION
CHARACTERISTICS
ZXMC3A17DN8
ISSUE 1 - OCTOBER 2005
3
SEMICONDUCTORS
ZXMC3A17DN8
ADVANCE INFORMATION
N-CHANNEL
ELECTRICAL CHARACTERISTICS
(at T
amb
= 25°C unless otherwise stated)
PARAMETER
STATIC
Drain-Source Breakdown
Voltage
Zero Gate Voltage Drain
Current
Gate-Body Leakage
Gate-Source Threshold
Voltage
Static Drain-Source On-State
Resistance
Forward
Transconductance
DYNAMIC
(3)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING
(2) (3)
Turn-On-Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Gate Charge
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
g
Q
gs
Q
gd
2.9
6.4
16
11.2
6.9
ns
ns
ns
ns
nC
V
DS
= 15V, V
GS
= 5V
I
D
= 3.5A
V
DS
= 15V, V
GS
= 10V
I
D
= 3.5A
V
DD
= 15V, I
D
=3.5A
R
G
≅
6.0 ,
V
GS
= 10V
C
iss
C
oss
C
rss
600
104
58.5
pF
pF
pF
V
DS
= 25V, V
GS
=0V
f=1MHz
(1) (3)
(1)
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
g
fs
30
0.5
100
1.0
0.050
0.065
10
V
A
I
D
= 250 A, V
GS
=0V
V
DS
=30V, V
GS
=0V
nA
V
V
GS
=±20V, V
DS
=0V
I
D
= 250 A, V
DS
=V
GS
V
GS
= 10V, I
D
= 7.8A
V
GS
= 4.5V, I
D
= 6.8A
S
V
DS
= 10V, I
D
= 7.8A
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
SOURCE-DRAIN DIODE
Diode Forward Voltage
(1)
(3)
(3)
12.2
1.7
nC
nC
nC
2.4
V
SD
t
rr
Q
rr
0.85
0.95
V
T
j
=25°C, I
S
= 3.2A,
V
GS
=0V
Reverse Recovery Time
18.8
14.1
ns
nC
Reverse Recovery Charge
(1)
(2)
(3)
T
j
=25°C, I
F
= 3.5A,
di/dt=100A/ s
Measured under pulsed conditions. Pulse width 300ms; Duty cycle 2%.
Switching characteristics are independent of operating junction temperature.
For design aid only, not subject to production testing.
ISSUE 1 - OCTOBER 2005
SEMICONDUCTORS
4
ADVANCE INFORMATION
ZXMC3A17DN8
P-CHANNEL
ELECTRICAL CHARACTERISTICS
(at T
amb
= 25°C unless otherwise stated)
PARAMETER
STATIC
Drain-Source Breakdown
Voltage
Zero Gate Voltage Drain
Current
Gate-Body Leakage
Gate-Source Threshold
Voltage
Static Drain-Source
On-State Resistance
(1)
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
g
fs
-30
V
I
D
= -250 A, V
GS
=0V
A
V
DS
= -30V, V
GS
=0V
V
GS
=±20V, V
DS
=0V
I
D
= -250 A, V
DS
=V
GS
V
GS
= -10V, I
D
= -3.2A
V
GS
= -4.5V, I
D
= -2.5A
-1.0
100
-1.0
nA
V
0.070
0.110
6.4
S
Forward
Transconductance
(1) (3)
DYNAMIC
(3)
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
SWITCHING
(2) (3)
Turn-On-Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Gate Charge
V
DS
= -15V, I
D
= -3.2A
C
iss
C
oss
C
rss
630
113
78
pF
pF
pF
V
DS
= -15V, V
GS
=0V
f=1MHz
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
g
Q
gs
Q
gd
1.7
2.9
29.2
8.7
8.3
ns
ns
ns
ns
nC
V
DS
= -15V, V
GS
= -5V
I
D
= -3.2A
V
DS
= -15V, V
GS
=
-10V
I
D
= -3.2A
V
DD
= -15V, I
D
= -1A
R
G
≅
6.0 ,
V
GS
= -10V
Total Gate Charge
Gate-Source Charge
Gate Drain Charge
SOURCE-DRAIN DIODE
Diode Forward Voltage
(1)
Reverse Recovery Time
(3)
Reverse Recovery Charge
NOTES:
(1)
(2)
(3)
(3)
15.8
1.8
2.8
nC
nC
nC
V
SD
t
rr
Q
rr
-0.85
-0.95
V
T
j
=25°C, I
S
= -2.5A,
V
GS
=0V
T
j
=25°C, I
S
= -1.7A,
di/dt=100A/ s
19.5
16.3
ns
nC
Measured under pulsed conditions. Pulse width 300ms; Duty cycle 2%.
Switching characteristics are independent of operating junction temperature.
For design aid only, not subject to production testing.
ISSUE 1 - OCTOBER 2005
5
SEMICONDUCTORS
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