DD-42900DC-200 datasheet, PDF - EEWORLD Datasheet

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DD-42900DC-200: DescriptionSerial I/O Controller, 2 Channel(s), 0.01220703125MBps, CMOS, CQIP40, CERAMIC, DIP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size155KB，8 Pages; ManufacturerData Device Corporation

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DD-42900DC-200 Overview

Serial I/O Controller, 2 Channel(s), 0.01220703125MBps, CMOS, CQIP40, CERAMIC, DIP-64

DD-42900DC-200 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Data Device Corporation
Parts packaging code	DIP
package instruction	QIP,
Contacts	64
Reach Compliance Code	compliant
Address bus width	12
boundary scan	NO
maximum clock frequency	16 MHz
Maximum data transfer rate	0.01220703125 MBps
External data bus width	16
JESD-30 code	R-CQIP-T40
JESD-609 code	e0
length	60.96 mm
low power mode	NO
Number of serial I/Os	2
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.08 mm
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	45.72 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1

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DD-42900

ARINC 429 Microprocessor Interface Device

This Preliminary data sheet provides detailed functional capabilities for product currently in prototype production.

These specifications are being provided to allow for electrical design, layout and operation.

DESCRIPTION

DDC's DD-42900 provides a com-

plete and flexible interface between a

microprocessor and ARINC 429 data

bus. The 42900 interfaces to a

processor through a 128 x 32 bit stat-

ic RAM as well as four 32 x 32 receive

FIFO's and two 32 x 32 transmit

FIFO's.The 42900 can be easily inter-

faced to 8- or 16-bit processors via a

buffered shared RAM configuration.

The 42900 supports four ARINC 429

Receive channels (Rx0, Rx1, Rx2

and Rx3) and each receive data inde-

pendently.The recieve data rates

(high or low speed) for channel Rx0

and Rx1 can be programmed inde-

pendently from Rx2 and Rx3.The

42900 can decode and sort data

based on the ARINC 429 Label and

SDI bits via the Data Match

Processor and store it in RAM and/or

FIFO's via the Data Store Processor.

The 42900 supports two ARINC 429

Transmit channels (Tx0 and Tx1) and

can transmit data independently.The

transmit data rate can be programmed

independently as well.There are two

32 x 32 bit FIFO's for each of the

transmitters for sending out data.

The device has the capability of pro-

gramming three general purpose

interrupts as well as generating an

interrupt based on an error condi-

tion.The general purpose interrupts

can be programmed to trigger other

external hardware.They can either be

LEVELtriggered or PULSE triggered.

The features built into the DD-42900

enable the user to off-load the host

processor and use that processing

time to do other more important

duties than polling the ARINC 429

Bus.The decoding and sorting of data

allows the user to gather data much

quicker that past designs. If the user

requires a microprocessor in the

avionics box, this device will enable a

clean and quick design.

128 X 16

STATIC RAM

DMT RAM

CTRL

DATA

ADDR

FEATURES

•

Four ARINC 429 Receive

Channels

•

128 x 32 Shared RAM Interface

•

Label and Destination Decoding

and Sorting

•

Two ARINC 429 Transmit Channels

•

Two 32 x 32 Transmit FIFO's

•

Interfaces Easily to 8- or 16-Bit

Microprocessors

•

Built-in Fault Detection Circuitry

128 X 32

STATIC RAM

Rx RAM

CTRL

DATA

ADDR

ARINC 429

RECEIVE 0

WRAPAROUND

ARINC 429

Rx LOGIC

Rx DATA

DATA

MATCH

PROCESSOR

DMP

DATA

STORE

PROCESSOR

Rx0 FIFO

32 WORDS

ADDR

ARINC 429

RECEIVE 1

ARINC 429

WRAPAROUND

Rx LOGIC

DATA

ADDR

DATA

ADDR

Rx1 FIFO

32 WORDS

ARINC 429

RECEIVE 2

WRAPAROUND

ARINC 429

Rx LOGIC

Rx2 FIFO

32 WORDS

ARINC 429

RECEIVE 3

WRAPAROUND

ARINC 429

Rx LOGIC

ADDR

DATA

Rx3 FIFO

32 WORDS

ARINC 429

TRANSMIT 0

ARINC 429

Tx LOGIC

Tx FIFO

32 WORDS

DATA

ARINC 429

TRANSMIT 1

ARINC 429

Tx LOGIC

Tx FIFO

32 WORDS

INTERRUPT

CONTROLLER

CPU INTERFACE

IRQ

DATA ADDR

MICROPROCESSOR

OR CPU

CONTROL

FIGURE 1. DD-42900 BLOCK DIAGRAM

1995 ILC Data Device Corporation

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