19-1991; Rev 0; 4/01
KIT
ATION
EVALU
BLE
AVAILA
Quad LVDS Line Driver
Features
o
Pin Compatible with DS90LV031A
o
Guaranteed 800Mbps Data Rate
o
250ps Maximum Pulse Skew
o
Conforms to TIA/EIA-644 LVDS Standard
o
Single +3.3V Supply
o
16-Pin TSSOP and SO Packages
General Description
The MAX9124 quad low-voltage differential signaling
(LVDS) line driver is ideal for applications requiring high
data rates, low power, and low noise. The MAX9124 is
guaranteed to transmit data at speeds up to 800Mbps
(400MHz) over controlled impedance media of approxi-
mately 100Ω. The transmission media may be printed
circuit (PC) board traces, backplanes, or cables.
The MAX9124 accepts four LVTTL/LVCMOS input levels
and translates them to LVDS output signals. Moreover,
the MAX9124 is capable of setting all four outputs to a
high-impedance state through two enable inputs, EN and
EN,
thus dropping the device to an ultra-low-power state
of 16mW (typ) during high impedance. The enables are
common to all four transmitters. Outputs conform to the
ANSI TIA/EIA-644 LVDS standard.
The MAX9124 operates from a single +3.3V supply and is
specified for operation from -40°C to +85°C. It is available
in 16-pin TSSOP and SO packages. Refer to the MAX9125/
MAX9126 data sheet for quad LVDS line receivers.
MAX9124
Ordering Information
PART
MAX9124EUE
MAX9124ESE
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TSSOP
16 SO
Applications
Digital Copiers
Laser Printers
Cell Phone Base
Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network
Switches/Routers
Backplane
Interconnect
Clock Distribution
Typical Applications Circuit
LVDS SIGNALS
MAX9126
MAX9124
T
X
115Ω
R
X
Pin Configuration
TOP VIEW
IN1 1
OUT1+ 2
OUT1- 3
EN 4
OUT2- 5
OUT2+ 6
IN2 7
GND 8
16 V
CC
15 IN4
14 OUT4+
LVTTL/LVCMOS
DATA INPUT
T
X
115Ω
R
X
LVTTL/LVCMOS
DATA OUTPUT
T
X
115Ω
R
X
MAX9124
13 OUT4-
12 EN
11 OUT3-
10 OUT3+
9
IN3
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
T
X
115Ω
R
X
TSSOP/SO
* Future product—contact factory for availability.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad LVDS Line Driver
MAX9124
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +4.0V
IN_, EN,
EN
to GND....................................-0.3V to (V
CC
+ 0.3V)
OUT_+, OUT_- to GND..........................................-0.3V to +3.9V
Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous
Continuous Power Dissipation (T
A
= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
Human Body Model, OUT_+, OUT_- ..............................±6kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, R
L
= 100Ω ±1%, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise
noted.) (Notes 1, 2)
PARAMETER
LVDS OUTPUT (OUT_+, OUT_-)
Differential Output Voltage
Change in Magnitude of V
OD
Between Complementary Output
States
Offset Voltage
Change in Magnitude of V
OS
Between Complementary Output
States
Output High Voltage
Output Low Voltage
Differential Output Short-Circuit
Current (Note 3)
Output Short-Circuit Current
Output High-Impedance Current
Power-Off Output Current
INPUTS (IN_, EN,
EN)
High-Level Input Voltage
Low-Level Input Voltage
Input Current
SUPPLY CURRENT
No-Load Supply Current
Loaded Supply Current
Disabled Supply Current
I
CC
I
CCL
I
CCZ
R
L
=
∞,
IN_ = V
CC
or 0 for all channels
R
L
= 100Ω, IN_ = V
CC
or 0 for all channels
Disabled, IN_ = V
CC
or 0 for all channels,
EN = 0,
EN
= V
CC
9.2
22.7
4.9
11
30
6
mA
mA
mA
V
IH
V
IL
I
IN
IN_, EN,
EN
= 0 or V
CC
2.0
GND
-20
V
CC
0.8
20
V
V
µA
V
OD
∆V
OD
V
OS
∆V
OS
V
OH
V
OL
I
OSD
I
OS
I
OZ
I
OFF
Enabled, V
OD
= 0
OUT_+ = 0 at IN_ = V
CC
or OUT_- = 0 at IN_
= 0, enabled
EN = low and
EN
= high, OUT_+ = 0 or V
CC
,
OUT_- = 0 or V
CC
, R
L
=
∞
V
CC
= 0 or open, OUT_+ = 0 or 3.6V, OUT_-
= 0 or 3.6V, R
L
=
∞
-10
-10
-3.8
0.90
-9
-9
10
10
Figure 1
Figure 1
Figure 1
Figure 1
1.125
250
368
1
1.25
4
450
25
1.375
25
1.6
mV
mV
V
mV
V
V
mA
mA
µA
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Quad LVDS Line Driver
SWITCHING CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, R
L
= 100Ω ±1%, C
L
= 10pF, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless
otherwise noted.) (Notes 4, 5, 6)
PARAMETER
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Pulse Skew (Note 7)
Differential Channel-to-Channel
Skew (Note 8)
Differential Part-to-Part Skew
(Note 9)
Differential Part-to-Part Skew
(Note 10)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Maximum Operating Frequency
(Note 11)
SYMBOL
t
PHLD
t
PLHD
t
SKD1
t
SKD2
t
SKD3
t
SKD4
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAX
CONDITIONS
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 4 and 5
Figures 4 and 5
Figures 4 and 5
Figures 4 and 5
400
0.1
0.1
0.35
0.35
MIN
0.8
0.8
TYP
1.42
1.44
0.02
MAX
2.0
2.0
0.25
0.35
0.8
1.2
0.7
0.7
5
5
5
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MAX9124
Note 1:
Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at T
A
= +25°C.
Note 2:
Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except
V
OD
.
Note 3:
Guaranteed by correlation data.
Note 4:
AC parameters are guaranteed by design and characterization.
Note 5:
C
L
includes probe and jig capacitance.
Note 6:
Signal generator conditions for dynamic tests: V
OL
= 0, V
OH
= 3V, f = 100MHz, 50% duty cycle, R
O
= 50Ω, t
R
≤
1ns, t
F
≤
1ns (0% to 100%).
Note 7:
t
SKD1
is the magnitude difference of differential propagation delay. t
SKD1
= |t
PHLD
- t
PLHD
|.
Note 8:
t
SKD2
is the magnitude difference of t
PHLD
or t
PLHD
of one channel to the t
PHLD
or t
PLHD
of another channel on the same
device.
Note 9:
t
SKD3
is the magnitude difference of any differential propagation delays between devices at the same V
CC
and within 5°C
of each other.
Note 10:
t
SKD4
is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 11:
f
MAX
signal generator conditions: V
OL
= 0, V
OH
= 3V, f = 400MHz, 50% duty cycle, R
O
= 50Ω, t
R
≤
1ns, t
F
≤
1ns (0% to
100%). Transmitter output criteria: duty cycle = 45% to 55%, V
OD
≥
250mV.
_______________________________________________________________________________________
3
Quad LVDS Line Driver
MAX9124
Typical Operating Characteristics
(T
A
= +25°C)
SINGLE-ENDED OUTPUT VOLTAGE
vs. LOAD RESISTANCE
(R
L
= 50Ω TO 400Ω)
MAX9124 toc01
SINGLE-ENDED OUTPUT VOLTAGE (V)
1.70
1.50
1.30
1.10
0.90
0.70
0.50
0.30
50
100
150
200
250
300
350
OUT_-
V
CC
= +3.6V
_V
CC
= +3.0V
OUT_+
SINGLE-ENDED OUTPUT VOLTAGE (V)
1.90
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0
0
D
OUT
+
V
CC
= +3.6V
_V
CC
= +3.0V
D
OUT
-
1000 2000 3000 4000 5000 6000 7000
R
L
(Ω)
400
R
L
(Ω)
Pin Description
PIN
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
4, 12
8
16
NAME
IN_
OUT_+
OUT_-
EN,
EN
GND
V
CC
LVTTL/LVCMOS Driver Inputs
Noninverting LVDS Driver Outputs
Inverting LVDS Driver Outputs
Driver Enable Inputs. The driver is disabled and in high impedance when EN is low and
EN
is high.
For other combinations of EN and
EN,
the outputs are active.
Ground
Power-Supply Input. Bypass V
CC
to GND with 0.1µF and 0.001µF ceramic capacitors.
FUNCTION
4
_______________________________________________________________________________________
MAX9124 toc02
2.10
SINGLE-ENDED OUTPUT VOLTAGE vs.
LOAD RESISTANCE
(R
L
= 0 TO 7kΩ)
Quad LVDS Line Driver
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The
LVDS standard uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI emissions and system susceptibility to
noise.
The MAX9124 is an 800Mbps quad differential LVDS
driver that is designed for high-speed, point-to-point,
and low-power applications. This device accepts
LVTTL/LVCMOS input levels and translates them to
LVDS output signals.
The MAX9124 generates a 2.5mA to 4.0mA output cur-
rent using a current-steering configuration. This current-
steering approach induces less ground bounce and no
shoot-through current, enhancing noise margin and sys-
tem speed performance. The driver outputs are short-
circuit current limited and enter a high-impedance state
when the device is not powered or is disabled.
The current-steering architecture of the MAX9124
requires a resistive load to terminate the signal and
complete the transmission loop. Because the device
switches current and not voltage, the actual output volt-
age swing is determined by the value of the termination
resistor at the input of an LVDS receiver. Logic states
are determined by the direction of current flow through
the termination resistor. With a typical 3.7mA output
current, the MAX9124 produces an output voltage of
370mV when driving a 100Ω load.
MAX9124
Table 1. Input/Output Function Table
ENABLES
EN
L
EN
H
INPUTS
IN_
X
L
H
Z
L
H
OUTPUTS
OUT_+
OUT_ -
Z
H
L
All other combinations
of ENABLE inputs
close to the device as possible, with the smaller valued
capacitor closest to V
CC
.
Differential Traces
Output trace characteristics affect the performance of
the MAX9124. Use controlled-impedance traces to
match trace impedance to the transmission medium.
Eliminate reflections and ensure that noise couples as
common mode by running the differential trace pairs
close together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90° turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a nominal differential
impedance of 100Ω. To minimize impedance disconti-
nuities, use cables and connectors that have matched
differential impedance.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables, such as twisted
pair, offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Termination
Because the MAX9124 is a current-steering device, no
output voltage will be generated without a termination
resistor. The termination resistors should match the dif-
ferential impedance of the transmission line. Output
voltage levels depend upon the value of the termination
resistor. The MAX9124 is optimized for point-to-point
interface with 100Ω termination resistors at the receiver
inputs. Termination resistance values may range
between 90Ω and 132Ω, depending on the characteris-
tic impedance of the transmission medium.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the LVTTL/LVCMOS
and LVDS signals from each other to prevent coupling.
Chip Information
TRANSISTOR COUNT: 2007
PROCESS: CMOS
Applications Information
Power-Supply Bypassing
Bypass V
CC
with high-frequency, surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
_______________________________________________________________________________________
5
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