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IDT7006S70GB

Description
Dual-Port SRAM, 16KX8, 70ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68
Categorystorage    storage   
File Size237KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
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IDT7006S70GB Overview

Dual-Port SRAM, 16KX8, 70ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68

IDT7006S70GB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codePGA
package instructionSPGA, PGA68,11X11
Contacts68
Reach Compliance Code_compli
ECCN code3A001.A.2.C
Maximum access time70 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-CPGA-P68
JESD-609 codee0
length29.464 mm
memory density131072 bi
Memory IC TypeDUAL-PORT SRAM
memory width8
Number of functions1
Number of ports2
Number of terminals68
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize16KX8
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeSPGA
Encapsulate equivalent codePGA68,11X11
Package shapeSQUARE
Package formGRID ARRAY, SHRINK PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Filter levelMIL-PRF-38535
Maximum seat height5.207 mm
Maximum standby current0.03 A
Minimum standby current4.5 V
Maximum slew rate0.3 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch1.27 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width29.464 mm
Base Number Matches1
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
Features
x
x
IDT7006S/L
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7006L
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7006 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
x
x
x
x
x
x
x
x
x
x
one device
M/S = H for
BUSY
output flag on Master,
M/S = L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
13L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
(1,2)
Address
Decoder
14
MEMORY
ARRAY
14
Address
Decoder
A
13R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2739 drw 01
SEPTEMBER 1999
1
DSC-2739/11

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