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74AUP1G240GM-H

Description
Buffer and line driver 3V single buf/LD inv 3S
Categorysemiconductor    logic   
File Size175KB,22 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74AUP1G240GM-H Overview

Buffer and line driver 3V single buf/LD inv 3S

74AUP1G240GM-H Parametric

Parameter NameAttribute value
MakerNXP
Product CategoryBuffers and Line Drivers
RoHSyes
logic seriesAUP
logical typeCMOS
Number of channels per chip1
polarityInverting
Supply voltage (maximum)3.6 V
Supply voltage (minimum)0.8 V
Maximum operating temperature+ 125 C
Minimum operating temperature- 40 C
Installation styleSMD/SMT
Package/boxXSON
EncapsulationReel
High level output current- 4 mA
Input bias current (maximum value)0.5 uA
Low level output current4 mA
Output type3-State
propagation delay time21.6 ns @ 1.1 V to 1.3 V or 12.3 ns @ 1.4 V to 1.6 V or 9.5 ns @ 1.65 V to 1.95 V or 7.1 ns @ 2.3 V to 2.7 V or 6.4 ns @ 3 V to 3.6 V
74AUP1G240
Low-power inverting buffer/line driver; 3-state
Rev. 2 — 13 September 2010
Product data sheet
1. General description
The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The
3-state output is controlled by the output enable input (OE). A HIGH level at pin OE
causes the output to assume a high-impedance OFF-state.
This device has the input-disable feature, which allows floating input signals. The inputs
are disabled when the output enable input OE is HIGH.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
μA
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
Input-disable feature allows floating input conditions
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

74AUP1G240GM-H Related Products

74AUP1G240GM-H 74AUP1G240GM-G
Description Buffer and line driver 3V single buf/LD inv 3S Buffer and line driver 3V single buf/LD inv 3S
Maker NXP NXP
Product Category Buffers and Line Drivers Buffers and Line Drivers
RoHS yes yes
logic series AUP AUP
logical type CMOS CMOS
Number of channels per chip 1 1
polarity Inverting Inverting
Supply voltage (maximum) 3.6 V 3.6 V
Supply voltage (minimum) 0.8 V 0.8 V
Maximum operating temperature + 125 C + 125 C
Minimum operating temperature - 40 C - 40 C
Installation style SMD/SMT SMD/SMT
Package/box XSON XSON
Encapsulation Reel Reel
High level output current - 4 mA - 4 mA
Input bias current (maximum value) 0.5 uA 0.5 uA
Low level output current 4 mA 4 mA
Output type 3-State 3-State
propagation delay time 21.6 ns @ 1.1 V to 1.3 V or 12.3 ns @ 1.4 V to 1.6 V or 9.5 ns @ 1.65 V to 1.95 V or 7.1 ns @ 2.3 V to 2.7 V or 6.4 ns @ 3 V to 3.6 V 21.6 ns @ 1.1 V to 1.3 V or 12.3 ns @ 1.4 V to 1.6 V or 9.5 ns @ 1.65 V to 1.95 V or 7.1 ns @ 2.3 V to 2.7 V or 6.4 ns @ 3 V to 3.6 V

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