CS42324
10-In, 6-Out, 2 Vrms Audio CODEC
D/A Features
Dual 24-bit Stereo DACs
Multi-bit Delta-Sigma Modulator
100 dB Dynamic Range (A-Wtd)
-90 dB THD+N
Integrated Line Driver
– 2 Vrms Output
– Single-Ended Outputs
Up to 96 kHz Sampling Rates
Stereo 7:1 Output Multiplexer
Volume Control with Soft Ramp
– 0.5 dB Step Size
– Zero Crossing Click-Free Transitions
Selectable Serial Audio Interface Formats
– Left- or Right-Justified, Up to 24-bit
– I²S Up to 24-bit
Selectable 50/15
μ
s De-Emphasis
Internal Analog Mute
Control Output for External Muting
Popguard
®
Technology
1.8 V to 3.3 V
3.3 V
A/D Features
Multi-bit Delta-Sigma Modulator
24-bit Conversion
Up to 96 kHz Sampling Rates
95 dB Dynamic Range (A-Wtd)
-88 dB THD+N
Stereo 5:1 Input Multiplexer
Digital Volume Control with Soft Ramp
–
0.5 dB Step Size
Selectable Serial Audio Interface Formats
–
–
Left-Justified
I²S
High-Pass Filter or DC Offset Calibration
See
System Features, General Description,
and Order-
ing information on
page 2.
3.3 V
9 V to12 V
PCM Serial
Interface
Level
Translator
Volume
Control/Mixer
Volume
Control/Mixer
Multibit
ΔΣ
Modulator
Multibit
ΔΣ
Modulator
Stereo DAC
5
7:1
MUX
Mute
Stereo Output 1
Serial Audio
Inputs
7:1
MUX
Mute
Stereo Output 2
Stereo DAC
5
7:1
MUX
Level Translator
SPI & I
2
C
Control Data
Interrupt
ADC Overflow
Reset
Mute
Stereo Output 3
5
Register Configuration
Internal Voltage
Reference
Mute
Control
Mute 1
Mute 2
Mute 3
Stereo Input 1
Stereo Input 2
Stereo Input 3
Stereo Input 4
Stereo Input 5
PCM Serial
Interface
Level
Translator
Serial Audio
Output
Volume
Control/High
Pass Filter
Low-Latency
Decimation
Filter
Multibit
Oversampling
Stereo ADC
5:1
MUX
Advance Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 2008
(All Rights Reserved)
JANUARY '08
DS721A6
CS42324
System Features
Direct Interface with 1.8 V to 3.3 V Logic Levels
Supports Asynchronous Serial Port Operation
–
–
Two Independent Clock Domains
ADC, DAC1, and DAC2 can be
Independently Assigned to the Two Clock
Domains
Each Serial Port Supports Master or Slave
Operation
General Description
The CS42324 is a highly integrated stereo audio
CODEC. The CS42324 performs stereo analog-to-
digital (A/D) and up to four channels of digital-to-analog
(D/A) conversion of up to 24-bit serial values at sample
rates up to 96 kHz.
A 5:1 stereo input multiplexer is included for selecting
between line-level inputs. The output of the input multi-
plexer is followed by an advanced 3rd-order, multi-bit
delta-sigma modulator and digital filtering/decimation.
Sampled data is transmitted by the serial audio inter-
face at rates from 4 kHz to 96 kHz, in either Slave or
Master Mode.
The D/A converter is based on a 5th-order multi-bit del-
ta-sigma modulator with an ultra-linear low-pass filter
and offers a volume control that operates with a 0.5 dB
step size. It incorporates selectable soft ramp and zero
crossing transition functions to eliminate clicks and
pops.
An integrated 7:1 stereo output multiplexer on each of
the three stereo 2 Vrms line-level outputs is used to se-
lect any of the 5 stereo analog inputs, for analog bypass
support, or the outputs of the 2 internal DACs. Each
2 Vrms output can be muted with the selectable analog
mute function.
Standard 50/15
μ
s de-emphasis is available for a
44.1 kHz sample rate for compatibility with digital audio
programs mastered using the 50/15
μ
s pre-emphasis
technique.
Integrated digital level translators allow easy interfacing
between the CS42324 and other devices operating over
a wide range of logic levels.
The CS42324 is available in a 48-pin LQFP package in
Commercial (-40°C to +85°C) and Automotive (-40°C to
+105°C) grades. The CDB42324 Customer Demonstra-
tion board is also available for device evaluation and
implementation suggestions. Please refer to
“Ordering
information” on page 71
for complete details.
–
Internal Digital Loopback
+3.3 V Analog Power Supply
+3.3 V Digital Power Supply
+9 V to +12 V High-Voltage Power Supply
Hardware or Software Mode Configuration
–
Supports I²C
®
and SPI
™
Software Interface
2
DS721A6
CS42324
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 8
1.1 Software Mode ................................................................................................................................. 8
1.2 Hardware Mode .............................................................................................................................. 10
1.3 Digital I/O Pin Characteristics ......................................................................................................... 12
2. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13
RECOMMENDED OPERATING CONDITIONS ................................................................................... 13
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 13
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ........................................................... 14
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ............................................................ 15
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16
ADC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ........................................................... 17
ADC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ............................................................ 18
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 19
ANALOG PASS-THRU CHARACTERISTICS ...................................................................................... 20
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 21
DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 21
SWITCHING CHARACTERISTICS - SERIAL AUDIO .......................................................................... 22
SWITCHING CHARACTERISTICS - SERIAL AUDIO (CONT.) ........................................................... 23
SWITCHING CHARACTERISTICS - SOFTWARE MODE - I²C FORMAT ........................................... 24
SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT .......................................... 25
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 26
4. APPLICATIONS ................................................................................................................................... 28
4.1 System Clocking ............................................................................................................................. 28
4.1.1 Master Clock ......................................................................................................................... 28
4.1.2 Synchronous / Asynchronous Mode ...................................................................................... 29
4.2 Serial Port Operation ...................................................................................................................... 29
4.2.1 Master Mode ......................................................................................................................... 30
4.2.2 Slave Mode ........................................................................................................................... 30
4.2.3 ADC, DAC1, and DAC2 clock selection ................................................................................ 31
4.2.4 High-Impedance Digital Output ............................................................................................. 31
4.2.5 Digital Interface Formats ....................................................................................................... 32
4.2.6 Synchronization of Multiple Devices ...................................................................................... 32
4.3 Analog-to-Digital Data Path ............................................................................................................ 33
4.3.1 ADC Analog Input Multiplexer ............................................................................................... 33
4.3.2 ADC Description .................................................................................................................... 33
4.3.3 High-Pass Filter and DC Offset Calibration ........................................................................... 34
4.3.4 Digital Attenuation Control ..................................................................................................... 34
4.4 Digital-to-Analog Data Path ............................................................................................................ 34
4.4.1 Digital Volume Control ........................................................................................................... 34
4.4.2 Mono Channel Mixer ............................................................................................................. 34
4.4.3 De-Emphasis Filter ................................................................................................................ 35
4.4.4 Internal Digital Loopback ....................................................................................................... 35
4.4.5 DAC Description .................................................................................................................... 35
4.4.6 Analog Output Multiplexer ..................................................................................................... 36
4.4.7 Output Transient Control ....................................................................................................... 36
4.4.8 Mute Control .......................................................................................................................... 37
4.5 Initialization ..................................................................................................................................... 37
4.5.1 Determining Hardware or Software Mode ............................................................................. 37
4.5.2 Hardware Mode Start-Up ...................................................................................................... 37
4.5.3 Software Mode Start-Up ........................................................................................................ 38
4.5.4 Initialization Flow Chart ......................................................................................................... 39
4.6 Device Control ................................................................................................................................ 40
DS721A6
3
CS42324
4.6.1 Hardware Mode ..................................................................................................................... 40
4.6.2 Software Mode - I²C Control Port .......................................................................................... 41
4.6.3 Software Mode - SPI Control Port ......................................................................................... 42
4.6.4 Memory Address Pointer (MAP) ............................................................................................ 43
4.7 Interrupts and Overflow .................................................................................................................. 43
5. REGISTER QUICK REFERENCE ........................................................................................................ 44
6. REGISTER DESCRIPTION .................................................................................................................. 46
6.1 Device I.D. and Revision Register (Address 00h) (Read Only) ...................................................... 46
6.1.1 Device I.D. (Read Only) ........................................................................................................ 46
6.1.2 Chip Revision (Read Only) .................................................................................................... 46
6.2 Mute Control (Address 01h) ........................................................................................................... 46
6.2.1 System MCLK Source ........................................................................................................... 46
6.2.2 Mute DAC2 Left-Channel ...................................................................................................... 46
6.2.3 Mute DAC2 Right-Channel .................................................................................................... 47
6.2.4 Mute DAC1 Left-Channel ...................................................................................................... 47
6.2.5 Mute DAC1 Right-Channel .................................................................................................... 47
6.2.6 Mute ADC Left-Channel ........................................................................................................ 47
6.2.7 Mute ADC Right-Channel ...................................................................................................... 47
6.3 Operational Control (Address 02h) ................................................................................................. 47
6.3.1 Global Power-Down .............................................................................................................. 47
6.3.2 INT Pin High/Low Active (INT_H/L) ....................................................................................... 48
6.3.3 Freeze ................................................................................................................................... 48
6.3.4 Tri-State SDOUT ................................................................................................................... 48
6.3.5 Tri-State Serial Port 1 ............................................................................................................ 48
6.3.6 Tri-State Serial Port 2 ............................................................................................................ 49
6.4 Serial Port 1 Control (Address 03h) ................................................................................................ 49
6.4.1 Serial Port 1 Master/Slave Select .......................................................................................... 49
6.4.2 Serial Port 1 Speed Mode ..................................................................................................... 49
6.4.3 MCLK1 Divider ...................................................................................................................... 49
6.4.4 Serial Port 1 MCLK source .................................................................................................... 49
6.5 Serial Port 2 Control (Address 04h) ................................................................................................ 50
6.5.1 Serial Port 2 Master/Slave Select .......................................................................................... 50
6.5.2 Serial Port 2 Speed Mode ..................................................................................................... 50
6.5.3 MCLK2 Divider ...................................................................................................................... 50
6.5.4 Serial Port 2 MCLK Source ................................................................................................... 50
6.6 ADC Clocking (Address 06h) .......................................................................................................... 50
6.6.1 ADC MCLK Source ............................................................................................................... 50
6.6.2 ADC Serial Port Source ......................................................................................................... 51
6.6.3 ADC Digital Interface Format (ADC_DIF) .............................................................................. 51
6.7 DAC1 Clocking (Address 07h) ........................................................................................................ 51
6.7.1 DAC1 MCLK Source ............................................................................................................. 51
6.7.2 DAC1 Serial Port Source ....................................................................................................... 51
6.7.3 DAC1 Digital Interface Format (DAC1_DIF) .......................................................................... 51
6.8 DAC2 Clocking (Address 08h) ........................................................................................................ 52
6.8.1 DAC2 MCLK Source ............................................................................................................. 52
6.8.2 DAC2 Serial Port Source ....................................................................................................... 52
6.8.3 DAC2 Digital Interface Format (DAC2_DIF) .......................................................................... 52
6.9 ADC Control (Address 0Ah) ........................................................................................................... 52
6.9.1 ADC High-Pass Filter Freeze ................................................................................................ 52
6.9.2 ADC Soft Ramp Control ........................................................................................................ 52
6.9.3 Analog Input Selection .......................................................................................................... 53
6.10 DAC1 Control (Address 0Bh) ....................................................................................................... 53
6.10.1 DAC1 De-Emphasis Control ................................................................................................ 53
6.10.2 DAC1 Single Volume Control .............................................................................................. 53
4
DS721A6
CS42324
6.10.3 DAC1 Soft Ramp Control .................................................................................................... 53
6.10.4 DAC1 Zero Cross Control ................................................................................................... 54
6.10.5 DAC1 Loop-Back ................................................................................................................. 54
6.10.6 DAC1 Invert Signal Polarity ................................................................................................. 54
6.10.7 DAC1 Channel Mixer ........................................................................................................... 54
6.11 DAC2 Control (Address 0Ch) ....................................................................................................... 55
6.11.1 DAC2 De-Emphasis Control ................................................................................................ 55
6.11.2 DAC2 Single Volume Control .............................................................................................. 55
6.11.3 DAC2 Soft Ramp Control .................................................................................................... 55
6.11.4 DAC2 Zero Cross Control ................................................................................................... 55
6.11.5 DAC2 Loop-Back ................................................................................................................. 56
6.11.6 DAC2 Invert Signal Polarity ................................................................................................. 56
6.11.7 DAC2 Channel Mixer ........................................................................................................... 56
6.12 AOUT1 Control (Address 0Dh) ..................................................................................................... 56
6.12.1 External Mute Control Pin ................................................................................................... 56
6.12.2 AOUT1 Select ..................................................................................................................... 56
6.13 AOUT2 Control (Address 0Eh) ..................................................................................................... 57
6.13.1 External Mute Control Pin ................................................................................................... 57
6.13.2 AOUT2 Select ..................................................................................................................... 57
6.14 AOUT3 Control (Address 0Fh) ..................................................................................................... 57
6.14.1 External Mute Control Pin ................................................................................................... 57
6.14.2 AOUT3 Select ..................................................................................................................... 58
6.15 ADCx Volume Control: ADCA (Address 10h) & ADCB (Address 11h) ......................................... 58
6.16 DAC1x Volume Control: DAC1A (Address 12h) & DAC1B (Address 13h) ................................... 58
6.17 DAC2x Volume Control: DAC1A (Address 14h) & DAC1B (Address 15h) ................................... 59
6.18 Interrupt Mode (Address 16h) ....................................................................................................... 59
6.19 Interrupt Mask (Address 17h) ....................................................................................................... 59
6.19.1 DAC2 Auto Mute Left Mask (DAC2_AMUTELM) ................................................................ 60
6.19.2 DAC2 Auto Mute Right Mask (DAC2_AMUTERM) ............................................................. 60
6.19.3 DAC1 Auto Mute Left Mask (DAC1_AMUTELM) ................................................................ 60
6.19.4 DAC1 Auto Mute Right Mask (DAC1_AMUTELM) .............................................................. 60
6.19.5 Serial Port 2 Clock Error Mask (SP2_CLKERRM) .............................................................. 60
6.19.6 Serial Port 1 Clock Error Mask (SP1_CLKERRM) .............................................................. 60
6.19.7 ADC Positive Overflow Mask (ADC_OVFLPM) ................................................................... 61
6.19.8 ADC Negative Overflow Mask (ADC_OVFLNM) ................................................................. 61
6.20 Interrupt Status (Address 18h) (Read Only) ................................................................................. 61
6.20.1 DAC2 Auto Mute Left Interrupt Status (DAC2_AMUTEL) ................................................... 61
6.20.2 DAC2 Auto Mute Right Interrupt Status (DAC2_AMUTER) ................................................ 61
6.20.3 DAC1 Auto Mute Left Interrupt Status (DAC1_AMUTEL) ................................................... 62
6.20.4 DAC1 Auto Mute Right Interrupt Status (DAC1_AMUTEL) ................................................. 62
6.20.5 Serial Port 2 Clock Error Interrupt Status (SP2_CLKERR) ................................................. 62
6.20.6 Serial Port 1 Clock Error Interrupt Status (SP1_CLKERR) ................................................. 62
6.20.7 ADC Positive Overflow Interrupt Bit (ADC_OVFLP) ............................................................ 62
6.20.8 ADC Negative Overflow Interrupt Bit (ADC_OVFLN) .......................................................... 63
7. GROUNDING AND POWER SUPPLY DECOUPLING ........................................................................ 64
8. ADC FILTER PLOTS ........................................................................................................................... 65
9. DAC DIGITAL FILTER RESPONSE PLOTS
................................................................................ 67
10. PARAMETER DEFINITIONS .............................................................................................................. 69
11. PACKAGE DIMENSIONS ................................................................................................................. 70
THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................................. 70
12. ORDERING INFORMATION .............................................................................................................. 71
13. REVISION HISTORY .......................................................................................................................... 71
DS721A6
5
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