Philips Semiconductors
Product specification
Triple 3-input NOR gate
FEATURES
•
Wide supply voltage range from 1.2 to 3.6 V
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Output capability: standard
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
I
CC
category: SSI.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
PARAMETER
propagation delay nA, nB, nC to nY
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
3.4
5.0
26
DESCRIPTION
74LVC27
The 74LVC27 is a high-performance, low power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74LVC27 provides the 3-input NOR function.
UNIT
ns
pF
pF
2004 Jan 13
2
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74LVC27
handbook, halfpage
handbook, halfpage
1A
1
VCC
14
13
12
1C
1Y
3C
3B
3A
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
MNA934
14 VCC
13 1C
12 1Y
1B
2A
2B
2C
2
3
4
5
6
7
Top view
GND
8
3Y
27
11 3C
10 3B
GND
(1)
11
10
9
9
8
3A
3Y
2Y
MNA973
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
handbook, halfpage
handbook, halfpage
1
2
13
≥
1
12
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
2B
2C
3A
3B
3C
MNA936
1Y
12
3
4
5
≥
1
6
2Y
6
9
10
≥
1
8
3Y
8
11
MNA935
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Jan 13
4
FPGA/CPLD
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