ORCA
®
ORSO42G5 and ORSO82G5
0.6 - 2.7 Gbps SONET Backplane Interface FPSCs
August 2005
Data Sheet
Introduction
Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5
devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and
ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbits/s and 20 Gbits/s respectively.
These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non-
SONET applications. The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6-
2.7Gbits/s SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable
FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already
been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces.
With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design-
ers can build a configurable interface using proven backplane driver/receiver technology. Designers can also use
the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The
ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbits/s backplane data connection and, with the
ORSO82G5, support both work and protection connections between a line card and switch fabric.
The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a
board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system
performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network
designers will benefit from using the backplane transceiver as a network termination device. Sister devices, the
ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet
(XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling,
streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi-
nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes
them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET
applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The
ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
Table 1. ORCA ORSO42G5 and ORSO82G5 Family – Available FPGA Logic
PFU
Columns
36
36
FPGA Max
User I/O
204
372
EBR
Blocks
2
12
12
EBR Bits
(K)
111
111
FPGA
System
Gates (K)
1
333-643
333-643
Device
ORSO42G5
ORSO82G5
PFU Rows
36
36
Total PFUs
1296
1296
LUTs
10,368
10,368
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with
40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%
EBR usage and 4 PLLs.
2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
orsox2g5_06.0
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
Sample Initialization Sequences – ORSO82G5......... 70
Reset Conditions........................................................ 72
SERDES Characterization Test Mode
(ORSO82G5 Only)............................................... 73
Embedded Core Block RAM ...................................... 74
Register Maps ............................................................ 76
Types of Registers ........................................ 77
Absolute Maximum Ratings ..................................... 108
Recommended Operating Conditions ...................... 108
SERDES Electrical and Timing Characteristics ....... 108
High Speed Data Transmitter...................... 109
High Speed Data Receiver.......................... 110
External Reference Clock ........................... 112
Pin Descriptions ....................................................... 113
Power Supplies ........................................................ 118
Power Supply Descriptions ......................... 118
Recommended Power Supply
Connections.......................................... 118
Recommended Power Supply Filtering
Scheme................................................. 118
Package Information ................................................ 120
Package Pinouts ......................................... 120
Package Thermal Characteristics Summary............ 148
Θ
JA
.............................................................. 148
ψ
JC
.............................................................. 148
Θ
JC
.............................................................. 148
Θ
JB
.............................................................. 148
FPSC Maximum Junction Temperature ...... 149
Package Thermal Characteristics ............... 149
Heat Sink Vendors for BGA Packages........ 149
Package Parasitics...................................... 149
Package Outline Drawings.......................... 150
Part Number Description.......................................... 151
Device Type Options................................... 151
Ordering Information ................................................ 151
Conventional Packaging ............................. 151
Lead-Free Packaging.................................. 152
Table of Contents
Introduction .................................................................. 1
Table of Contents......................................................... 2
Embedded Function Features...................................... 3
Programmable Features .............................................. 4
Programmable Logic System Features........................ 5
Description ................................................................... 6
What Is an FPSC? .......................................... 6
FPSC Overview............................................... 6
FPSC Gate Counting ...................................... 6
FPGA/Embedded Core Interface .................... 6
ispLEVER Development System..................... 7
FPSC Design Kit ............................................. 7
ORSO82G5/42G5 FPGA Logic Overview....... 7
ORCA Series 4 FPGA Logic Overview ........... 7
PLC Logic........................................................ 8
Programmable I/O........................................... 8
Routing............................................................ 9
System Level Features ................................... 9
MicroProcessor Interface ................................ 9
System Bus ..................................................... 9
Phase-Locked Loops ...................................... 9
Embedded Block RAM .................................. 10
Configuration................................................. 10
ORSO42G5 and ORSO82G5 Overview .................... 10
Embedded Core Overview ............................ 11
ORSO42G5 and ORSO82G5 Main
Operating Modes - Overview.................. 12
Embedded Core Functional Blocks -
Overview................................................. 13
Loopback - Overview .................................... 14
FPSC Configuration - Overview .................... 15
ORSO42G5 and ORSO82G5 Embedded Core
Detailed Description ............................................ 16
Top Level Description - Transmitter (TX)
and Receiver (RX) Architectures ............ 16
Detailed Description - SERDES Only
Mode....................................................... 19
32:8 MUX ...................................................... 21
SONET Mode Operation –
Detailed Description ............................... 24
SONET Mode Transmit Path ........................ 30
SONET Mode Receive Path ......................... 33
Cell Mode Detailed Description..................... 49
Cell Mode Transmit Path............................... 52
Cell Mode Receive Path................................ 56
Cell Extractor................................................. 56
Receive FIFO ................................................ 57
Input Port Controllers .................................... 57
IPC Receive Cell Mode Timing
Core/FPGA ............................................. 59
Reference Clock Requirements .................... 67
Sample Initialization Sequences – ORSO42G5......... 69
2
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
Embedded Function Features
• High-speed SERDES programmable serial data rates of 0.6 Gbits/s to 2.7 Gbits/s.
• Asynchronous operation per receive channel (separate PLL per channel).
• Transmit pre-emphasis (programmable) for improved receive data eye opening.
• Provides a 10 Gbits/s backplane interface to switch fabric using four work and, with the ORSO82G5, four protect
2.5 Gbit/s links. Also supports port cards at rates between 0.6 Gbits/s and 2.7 Gbits/s.
• Allows wide range of applications for SONET network termination, as well as generic data moving for high-speed
backplane data transfer.
• No knowledge of SONET/SDH needed in generic applications. Simply supply data (75 MHz-168.75 MHz clock)
and at least a single frame pulse.
• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
clocks.
• Four- or eight-channel HSI functions provide 2.7 Gbits/s serial user data interface per channel for a total chip
bandwidth of >10Gbits/s or >20 Gbits/s (full duplex).
• SERDES has low-power CML buffers and support for 1.5V/1.8V I/Os.
• SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating
state.
• Powerdown option of SERDES HSI receiver and/or transmitter on a per-channel basis.
• Ability to mix half-rate and full-rate between the channels with the same reference clock.
• Ability to configure each SERDES block independently with its own reference clock.
• STS-48 framing in SONET mode.
• Programmable enable of SONET scrambler/descrambler, A1/A2 insertion and B1 generation and checking.
• Insertion and checking of link assignment values to facilitate interconnection and debugging of backplanes.
• Optional AIS-L insertion during loss-of-frame.
• Optional RDI-L insertion to indicate remote far-end defects for maintenance capabilities.
• SPE signal marks payload bytes in SONET mode.
• Frame alignment across multiple ORSO42G5 and ORSO82G5 devices for work/protect switching at STS-
768/STM-256 and above rates.
• Supports transparent mode where Transport OverHead (TOH) bytes are user-generated in the FPGA.
• Supports two modes of in-band management and configuration with TOH byte extraction/insertion by the
Embedded core. A1/A2 and B1 insertion can be independently enabled.
– AUTO_SOH where the embedded core inserts the A1/A2 framing bytes, performs the B1 calculation and
inserts the B1 byte. All other bytes are passed through unchanged from the FPGA logic as in transparent
mode.
– AUTO_TOH where all of the overhead bytes are set by the embedded core. Most of the bytes are set to zero.
At the receive side, all of the TOH bytes except those set to a non-zero value can be ignored.
• Optional A1/A2 corruption, B1 byte corruption, and K2 byte corruption for system debug purposes.
• Built-in boundary scan (
IEEE
® 1149.1 and 1149.2 JTAG), including the SERDES interface.
• FIFOs align incoming data across all eight channels (ORSO82G5 only), groups of four channels, or groups of
two channels. Optional ability to bypass alignment FIFOs for asynchronous operation between channels is also
provided. (Each channel includes its own recovered clock and frame pulse).
3
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
• Optional cell processing blocks included. Cell processing includes cell creation, extraction, idle cell insertion and
deletion asynchronous from line rates. Four cell sizes supported:
– 77 bytes per cell (75 bytes of data payload)
– 81 bytes per cell (79 bytes of data payload)
– 85 bytes per cell (83 bytes of data payload)
– 93 bytes per cell (91 bytes of data payload)
• Automatic cell striping across either pairs of SERDES links or, for the ORSO82G5, all eight SERDES links.
• Addition of two 4K X 36 dual-port RAMs accessible by the programmable logic.
Programmable Features
• High-performance programmable logic:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 400K usable system gates.
– Meets multiple I/O interface standards.
– 1.5V operation (30% less power than 1.8V operation) translates to greater performance.
• Traditional I/O selections:
– LVTTL (3.3V) and LVCMOS (2.5V, and 1.8V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3V PCI compliance.
– Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path.
• New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off), internal parallel termination (100
Ω
)
is also supported for these I/Os.
• New capability to (de)multiplex I/O signals:
– New DDR on both input and output.
– New 2x and 4x downlink and uplink capability per I/O.
• Enhanced twin-block Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-
dently, plus one extra for arithmetic operations.
– New register control in each PFU has two independent programmable clocks, clock enables, local set/reset,
and data selects.
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4
→
1 MUX, new 8
→
1 MUX,
and ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, configurable as single-port or dual-port. Create large, fast RAM/ROM blocks (128 x 8
in only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
internal routing which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
4
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efficient performance.
• Supplemental Logic and Interconnect Cell (SLIC) provides eight 3-statable buffers, up to a 10-bit decoder, and
PAL
™-like AND-OR-Invert (AOI) in each programmable logic cell.
• New 200 MHz embedded block-port RAM blocks,
2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be configured as:
– 1—512 x 18 (block-port, two read/two write) with optional built in arbitration.
– 1—256 x 36 (dual-port, one read/one write).
– 1—1K x 9 (dual-port, one read/one write).
– 2—512 x 9 (dual-port, one read/one write for each).
– 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
– Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1Kx 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-
in system registers that act as the control and status center for the device.
• Built-in testability:
– Full boundary scan (
IEEE
1149.1 and Draft 1149.2 JTAG).
– Programming and readback through boundary scan port compliant to
IEEE
Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
– New temperature-sensing diode.
• Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock
modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of
the input frequency up to 64x and division of the input frequency down to 1/64x possible.
• New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route.
This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide
reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
• PCI local bus compliant for FPGA I/Os.
Programmable Logic System Features
• Improved
PowerPC
®
860 and
PowerPC
II high-speed synchronous MicroProcessor Interface can be used for
configuration, readback, device control, and device status, as well as for a general-purpose interface to the
FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous
PowerPC
processors
with user-configurable address space provided.
• New embedded system bus facilitates communication among the MicroProcessor Interface, configuration logic,
Embedded Block RAM, FPGA logic, and embedded standard cell blocks.
• Variable size bused readback of configuration data with the built-in MicroProcessor Interface and system bus.
• Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
• New clock routing structures for global and local clocking significantly increases speed and reduces skew.
• New local clock routing structures allow creation of localized clock trees.
• Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
5
Analogue and Mixed Signal
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