EEWORLDEEWORLDEEWORLD

Part Number

Search

A3PN060-Z1QNG100I

Description
fpga - field programmable gate array 60k system gates proasic3 nano
CategoryProgrammable logic devices    Programmable logic   
File Size4MB,106 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Environmental Compliance
Download Datasheet Parametric View All

A3PN060-Z1QNG100I Overview

fpga - field programmable gate array 60k system gates proasic3 nano

A3PN060-Z1QNG100I Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerActel
package instruction8 X 8 MM, 0.85 HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-100
Reach Compliance Codeunknown
JESD-30 codeS-PBCC-B100
Number of entries71
Number of logical units1536
Output times71
Number of terminals100
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQCCN
Encapsulate equivalent codeLCC100,.32SQ,20
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.5,1.5/3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBUTT
Terminal pitch0.5 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
Revision 8
ProASIC3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
®
Advanced I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
Low Power
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18 organization)
Low Power ProASIC 3 nano Products
1.5 V Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
®
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Enhanced Commercial Temperature Range
• –20°C to +70°C
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
ProASIC3 nano-Z Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
2
4,608-Bit Blocks
2
FlashROM Kbits
Secure (AES) ISP
2
Integrated PLL in CCCs
2
VersaNet Globals
I/O Banks
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
Package Pins
QFN
VQFP
10,000
86
260
1
4
2
34
34
QN48
15,000
128
384
1
4
3
49
QN68
20,000
172
520
1
4
3
49
52
QN68
A3PN010
A3PN015
A3PN020
A3PN030Z
1
30,000
256
768
1
6
2
77
83
QN48, QN68
VQ100
A3PN060
A3PN125
A3PN250
A3N250Z
250,000
2,048
6,144
36
8
1
Yes
1
18
4
68
68
A3PN060Z A3PN125Z
60,000
512
1,536
18
4
1
Yes
1
18
2
71
71
125,000
1,024
3,072
36
8
1
Yes
1
18
2
71
71
VQ100
VQ100
VQ100
Notes:
1. A3PN030 is available in the Z feature grade only.
2. A3PN030 and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the
ProASIC3
and
ProASIC3E
datasheets.
† A3PN030 and smaller devices do not support this feature.
April 2010
© 2010 Actel Corporation
I
A Hong Kong pharmaceutical group company is recruiting embedded software development engineers (Shanghai)
Job Responsibilities: Responsible for the company's new product development and trial production. Development and design of single-chip microcomputers and embedded products. Candidate Requirements: 1)...
alert4 Embedded System
Coherent multiprocessing on a single chip (Figure)
[b]With the advent of SoC design elements such as the MIPS32 1004K Coherent Processing System (CPS), on-chip symmetric multiprocessing (SMP) with a single operating system has become a real design cho...
咖啡不加糖 MCU
Talk about the precautions for PCB layout in switching power supply
[b](1) Let's talk about the placement of Y capacitors. 1. The general pitch of Y capacitors is 10mm, leaving a pad, and the gap in the middle is 8mm. It is best not to run a line in the middle. 2. No ...
qwqwqw2088 PCB Design
Changsha University of Science and Technology E-sports Summer Training Camp
[i=s] This post was last edited by paulhyde on 2014-9-15 08:53 [/i] The photo is not good, it was taken with a mobile phone...
longhaozheng Electronics Design Contest
Quickly identify the fake security monitoring devices with pictures
We have investigated the existence of "parallel imports" and "counterfeit products" in the security industry and found that the security market is just like other electronic product markets, with mixe...
xyh_521 Industrial Control Electronics
Share TI Texas Instruments TMS320C6416 DSP chip self-test program
[font=Microsoft Yahei, Hei, Tahoma, SimHei, sans-serif][size=16px][b]TI Texas Instruments TMS320C6416 DSP chip self-test program[/b][/size][/font]...
Jacktang Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1786  413  1799  498  1719  36  9  37  11  35 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号