INTERFACE TIMING CHARACTERISTICS (applies to all parts
6, 10
)
Clock Frequency
f
CLK
Input Clock Pulse Width
t
CH
, t
CL
t
CSS
CS to CLK Setup Time
t
CSH
CS Rise to CLK Hold Time
t
UDS
U/D to Clock Fall Setup Time
Conditions
Min
Typ
1
50
Clock level high or low
10
10
10
10
Max
Unit
MHz
ns
ns
ns
ns
1
2
Typicals represent average readings at 25°C, V
DD
= 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
NL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use V
DD
= V.
10
All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
V
DD
= 5 V.
INTERFACE TIMING DIAGRAMS
CS = LOW
U/D = HIGH
CLK
R
WB
Figure 2. Increment R
WB
CS = LOW
U/D = 0
CLK
Figure 3. Decrement R
WB
1
CS
0
t
CSS
t
CL
t
CH
t
CSH
1
CLK
0
t
UDS
1
U/D
0
t
S
R
WB
04419-0-006
Figure 4. Detailed Timing Diagram(Only R
WB
Decrement Shown)
Rev. 0 | Page 4 of 16
04419-0-005
R
WB
04419-0-004
AD5227
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
V
DD
to GND
V
A
, V
B
, V
W
to GND
Digital Input Voltage to GND (CS, CLK, U/D)
Maximum Current
I
WB
, I
WA
Pulsed
I
WB
Continuous (R
WB
≤ 5 kΩ, A open)
1
I
WA
Continuous (R
WA
≤ 5 kΩ, B open)
1
I
AB
Continuous
(R
AB
= 10 kΩ/50 kΩ/100 kΩ)
1
Operating Temperature Range
Maximum Junction Temperature (T
J
max)
Storage Temperature
Lead Temperature (Soldering, 10 s – 30 s)
Thermal Resistance
2
θ
JA
Rating
−0.3 V, +7 V
0 V, V
DD
0 V, V
DD
±20 mA
±1 mA
±1 mA
±500 µA/
±100 µA/±50 µA
−40°C to +105°C
150°C
−65°C to +150°C
245°C
230°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. V
DD
= 5 V.
2
Package power dissipation = (T
J
max – T
A
) / θ
JA
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
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