ANALOG
DEVICES
:
FEATURES
DACl138
18'Bit Resolutionand Accuracv (38gV, 1 Part in 262,1441
Nonlinearity1/2LSB max (DACI 138K)
ExcellentStability
in
Settlinsto 1/2LSB (0.0002%) 1ops
Sem
Hermetically-Sealed iconductors
DAC1136
16-Bit Resolutionand Accuracy n52PV,1 Part in 65,536)
Low Cost
1
N o n l i n e a r i t y / 2 L S Bm a x ( D A C I 1 3 6 K ,L )
in
Settlingto 1/2LSB max (0.0008%) Qrs
I
D E G L I T C H E RV
DAC Glitches
Eliminates
Assembly
on
Available DACl 136/1138 Card-Mounted
GENERAL DESCRIPTION
culrent or
self-contained
6/1138 arecomplete
The DAC113
with
converters
voltageoutput modular digital-to-analog
1.6and 18 bits'
of
and
resolutions accuracies
currentsources
combineprecision
The DAC1136/1138
to
switches producea very linear
steering
with state-of-the-art
with TTL
are
output. Inputsto theseconverters compatible
havea currentoutput of -2mA full scale.
The converters
levels,
A voltageoutput can be obtainedby connectingthe internal
amplifier to the current output by meansof jumpers. By using
jumpers, usercan selectany one of the fol-
the
additional
:
o u t p u t r a n g e sO t o + 5 V , 0 t o + 1 0 V , l 5 V , o r t 1 0 V .
lowing
Assemblies.
on
The DAC1136/1138 areavailable Card-Mounted
options include' input codes,
In this configuration,selectable
output amplifiers,and a high speedtransient-suppressing
DeglitcherModule,DeglitcherIV.
DACS
WHERETO USEHIGH RESOLUTION
for
accuracy a broad
The DAC1136lll38 deliverexceptional
The
test and instrumentationapplications.
rangeof ciisplay,
of
DAC1136,with a resolution 16 bits or 1 part in 65'536'
of
and thc DAC1138with a resolution 18 bits or 1 Part in
requiringwide
262,1++are ideally suitedfor applications
and
dynamicrangemeasurement control. Applicationsinclude
auto-
high resolutionCRT displays,
data acquisitionsystems'
f
testing,p hoto-typesetting,requency
matic semiconductor
and nuclearreactorcontrol.
synthesis
16-
Resolution and18-Bit
High
Convefte
Digital-to-Analog
:.]:;*
.it
CERTIFICATE OF CALIBRATION
Each DACl138 has been calibrated with equipment and
methoCs that are traceable to the National Bureeu of Stand-
ards (NBS). A Certificate of Performance is sent with each
unit, which includes linearity test data.
MSB
atT2
8tT3
B I T4
B I T5
B I T6
B I T7
B I T8
B I T9 1 6
BIT1O 1 7
BIT 11 1 8
BIT12 1 9
8tr 13
gtr 14
stT 15
BIT16
*BrT17
23
24
26
27
7I
70
69
68
ZERO
ADJUST
5k SENSE
CURRENT
OUT
l0k sENsE
53 REFIN
5 2 R E FO U T
49 GAIN
48 GAIN
47 AMP OUT
46 tsIPOLAR
OFFSET
OUT
E
AMP IN
' L : : 1 8 29
30
,r 5v 32
COMMON 34
* D A C l ] 3 8O N L Y
Figure L Block Diagram and Pin Designations
Information {urnished by Analog Devicesis believedto be accurate
a n d r e l i a b l e . H o w e v e r , n o r e s p o n s i b i l i t yi s a s s u m e db y A n a l o g D e v i c e s
f o r i t s u s e ; n o r f o r a n y i n f r i n g e m e n t so f p a t e n t so r o t h e r r i g h t s o f t h i r d
p a n i e s w h i c h m a y r e s u l t f r o m i t s u s e . N o l i c e n s ei s g r a n t e d b y i m p l i c a -
i i o n o r o t h e r w i s e u n d e r a n y p a t e n t o r p a t e n t r i g h t so f A n a l o g D e v i c e s .
02062 U.S.A.
P.O. Box 28O; Norwood, Massachusetts
Twx: 710/394'6577
Tel: 617132947O0
NORWOODMAS
Cables:
ANALOG
924491
Telex:
noted)
IFICATI(INS
heropiions asllodule- otherwise
ierldeglitc
same
udgss
SPEC
Smllif
. :- "'-^ _*..
I
DACll36 Module
K
l6
L
(typical + 25"C,
power
noted;
for
rated
supplies
unless
othenyise specificationsmounting
cardwith
@
DACll36 on Mounting Card with
Amplilier/Deglitcher Options.
RESOLUTION,
BITS
ACCURACY
IntegralNonlinearity
Differential Nonlinearity
Gain and Offset Error (ExternallyAdjustable)
ILSBmax i
:: I/2LSB max
I * llzLSBmax
lLSBmax
t I/2LSB max
| * lz2LSB-a*
i
Gain, offset and glitch-nulling adjustments
provided on the mounting card.
ANALOGOUTPUT
UnipolarMode
Bipolar
Mode
Output Range(Pin Selectable)
DIGITAL INPUTS
INPUTCODES
Unipolar Mode
Bipolar Mode
2mA to OmA
- lmAto + lmA
0to +5V,0to + l0v, -!5v, t l0V
TTL/CMOS; SeeFigure 2
Binary (COMP BIN)
Complementary
Complementary
Offset Binary (COMP OBIN)
None
BIN, COMP BIN, 2's COMP, COMP 2's COMP
|
OBIN, COMP OBIN
I
PLUS MAGBIN, COMP SIGN PLUS MAG BIN
iSIGN
I
One standard series74LS load, leading-edge
triggered,pulsewidth l00ns minimum
INPUT
STROBE
DYNAMIC CHARACTERISTICS
S e t t l i n g T i n e t ol i 2 L S B
Current
Full Scale
Step
LSB Step
Voltage
Unipolar(l0V Step)
Bipolar (20V Step)
LSB Step
Slcw Rate
IEMPERATURE COEFFICIENTS
ppm of FStu"C)r
InregralNonlinearity
DifferentialNonlinearity
Gain iExcluding Vp1;1.)
0ffsct
Unipolar Mode
Bipolar,\lode
VoltageOutput, Only
VoltageOutput, Only
90ps
250ps
8ps
lV/ps
80ps
90ps
8ps
2Vlps
45ps
60ps
8ps
6V/ps
25ps
30ps
8ps
20V/ps
t l.5 max
t 1 . 5m a x
t8max
t 0.5
STABILITY,LONGTERM
0
o
r
, p p m f F S R1 , 0 0 h r s . ) 2
BipolarMode l
Output Current (BV -- l0OkHz)
(
O u t p u tV o l t a g e B W - 0 . l - l O H z )
, , 0 \ ' i A l I I ' s C o d e ;" Z E R O " )
,, 5\'iMSB = 0Code;"HalfScale")
' , l 0 \ ' r A l I 0 ' sC o d e l" F u l l S c a l e " )
0 . 5 n Am s
r
4pV pk-pk
6pV pk-pk
9pV pk-pk
30pVrms
VoltageOutput, Only
40pVrms
I
35pVrms
Fl,x Drift
Currcnt Output (pin 69)
!oltage Protection
Source
Resistance
Unipolar Mode
Bipolar Mode
Source
Capacitance
RhFERENCE VOLTAGE (VRr,r.)
!oltagc I Z()r-r :200O)
\oisc.BV':0.1-lOHz)
Tcmpco
t 2mV max
t l00pV
t l0pV/"C
via Internal SchottkyDiodes
t 50pV
:r 5pV/"C
:t20pV
:t0.lpV/"C
!
i
tl0opv
* tSrrVfC
>33ko
>5ko
I 50pF
(Maximum
+ 6.000V
Error,
3pVpk-pk
5ppm/'C
9mA
r 30mA
80dB
t l/4LSBperVoltAV5
pbv nn il'pi;li
REaLTTEEMENTS1*
:t 38mA
l00dB
- iV dc. I 59i,
: l5\'dc. t5o/o
PoU'ER SUPPLY REJECTION ( t I 5V dc)
Gain or Offset vs. FSR
Dilfcrential Nonlinearity
-i*r
rnolirsMAl-*-
0to +70'C
- 55"C + 85"C
ro
5%to95%,
Noncondensing
- 55'C + 85'C
ro
Operating'lemperaturc
-femperaturc
Storage
Humiditv
I - : s ' c t o+ s s ' c
55"C + 85'C
ro
NOTES
r.Vaximum temperature ccfficients guaranteed from l5'C to 35'C, (ypical from 0 to + 70'C.
'RecommendedDNL calibrationcheck: 6 months.
rRecommendedPower Supply: Analog Devices Model 923.
wrthout notice.
catrons
subiectro change
Specrfi
-2-
IFt 0NS'y.'[lfi:#
SPECCAT|
DACll3S
Module
for
card
otherwise specificationsmounting with
noted;
supplies
unless
+ 25"C,
power
rated
noted)
unless
same m0dule otherwise
as
DACI138 on Mounting Card with
Amplifi er/Deglitcher Optrons.
Deglitcher IV
Low Drift 2l4L
{
(Internal AD542K)
w,/woDeglitcher
i
RESOLUTION,BITS
ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Gain and Offset Error (Externally Adiustable)
l/2LSB max
l/2LSB max
i
**1-*-**"--
ANALOGOUTPUT
UnipolarMode
Mode
Bipolar
VoltageOutput Range(Pin Selectable)
DIGITAL INPUTS
- 2mA to OnA
lmA to + lmA
0ro + 5V,0to + lOV,15v, a lov
l
I
I
Galn, oftset and glitch-nulling adiustments
provided on the mounting card.
I
I
INPUTCODES
UnipolarMode
Mode
Bipolar
INPUT
STROBE
DYNAMIC CHARACTERISTICS
SenlingTimeto li2LSB
Current
Full Scale
Step
LSB Step
Voltage
Unipolar (l0V Step)
Bipolar (20V Step)
LSB Step
SlewRate
TEMPERATURE COEFFICIENTS
(ppm of FSR7"C)
Integral Nonlinearity
Differential Nonlinearity
Gain (ExcludingVpsp)
Offset
Unipolar Mode
Bipolar Mode
STABILITY, LONGTERM
(ppm of FSRJl,000hrs.)'
Gain (Excluding Vqsil
Offset
NOISE (Include Vp6p; Double for
Bipolar Mode)
OutputCurrent (B'V - l00kHz)
Output Voltage(BrJfl= 0. l-l0Hz)
( a 0 V ( A l I I ' s C o d e ;" Z E R O " )
(r 5V(MSB = 0Code;"Half Scale")
(rr10V(Al I0'sCode; "Full Scale")
OutputVoltage(BW = l00kHz)
VOLTAGE COMPLIANCE (Amolifi er
Max Ee5 Allowed for
Rated Accuracy
Initial Eos (FactoryAdi.)
E65 Drift
Current Output (pin 69)
Voltage Protection
SourceResistance
Unipolar Mode
Bipolar Mode
SourceCapacitance
Voltage (Zour -200Q)
Noise(BrV = 0.1-l0Hz)
Tempco
l0ps
8ps
I75ps
l40ps
l8ps
2Vlgs
80ps
90ps
I 8ps
Mlrs
VoltageOutput, Only
VoltageOutput, Only
!
J
I
45ps
60ps
l8ps
I
- "- 9Y/p:*
t 0.3
t 0.4
t 0.8
a 0.5
:tl
:t0.5
I
I
tO.l
0 . 5 n Am s
r
4pV pk-pk
6pV pk-pk
9pVpk-pk
30pVrms
Voltage Output, Only
40pV rms
t 200pVmax
* l00pV
* l0pV/'C
viaInternalSchottky
Diodes
>33k()
>5ko
l50pF
+0.024V)
+6.000V(MaximumError,
3pVpk-pk
5ppm/"C
,t 50pV
t 5pVi'C
:t 2OpV
* 0. I pV/'C
I
i
l
POWER
SUPPLY
REQUIREMENTS,
+5Vdc,5%
t
t l 5 V d c ,a 5 %
PO!/ER SUPPLY REJECTION( t l5V dc)
Gain or Offset vs. FSR
Differential Nonlinearitv
Operating Temperature
StorageTemperature
Humidity
NOTES:
rRecommended
DNL calibrarion check: 6 motrrhs.
2RecommendedPowerSupply Analog
Devices: Model 923
Specificatrons
wrrhournorice.
subjecr change
ro
80dB
i I/4LSB
Volt AV
0 to + 70'C
55'C + 85"C
ro
5% to 95%,
- 55'C + 85"C
ro
55'C to + 85'C
-3-
Curves*
Characteristic
0.1
.g
INPUT CONSIDERATIONS
may be driven by TTL or CMOS as
The DAC113611138
shownin Figure 2. Note that the TTL input is shownwith
"totem pole" TTL gate and oPen
inputs for both a direct
"pull-up") configurations.
collector (or
% L S B 1 2B I T S
@
E o.o1
:R
I
14
u
s
J
F
g
l5
z
0.001
16
17
%LSB 18 B|TS
@
2a. TTL Totem Polet
2b. Switch or RelaY lnqut"
1ps
10ps
lo0gs
SETTLING IME
T
1ms
10ms
Settling Time (Voltage Output) vs. /o-of'Full-Scale-
(+l}v +
Enir for 20VOutputStep
-l?v)
0.1
G
TO
ON
HAVE INTERNALlOKOPULL-UP EACHINPUT 3.8V.
CONVEFTERS
THE
IS
WHENSWITCH OPEN,
OR
SV{ITCH RELAYTO GROUND.
2. USESPST
UP
INTERNAL
lOKOWILL PULL INPUT TO 3.8V.
.,...,,
rrL
w,rH""1i..l1"1i"3::.."^.
, FoB opEN
Figure 2. lnput Connections
@
% L S B 1 2B | T S
E 0.0r
;e
I
14
G
t
15
16
17
% L S B 1 8B r r S
@
0.0(X)1
llls
'l0ps
100Ps
T
SETTLING IME
lms
10ms
$ o.oor
z
l
F
4
Settling Time (Voltage Output) vs. %'of'Full-Scale'
+l?V)
Error for 10V Ouput Step(0V *
o.1
g
AND GUARDING
OUTPUT CONNECTIONS
voltage
for
6/1138 output connections various
The DAC113
are
ranges shown in Figure 3.
Sincean LSB is only 38pV (at 10 volts full scalefor the
to
DAC1138),caremust be exercised properlyguard the
current output of the converterfrom leakagecurrent. Any
madeto the DAC's current output (pin 69)
connection
should be guarded.Suggested
Printed circuit board guarding
Assemblies
is shownin Figure 3. The optional Card-Mounted
for
of the DACl136lll38 havebeencarefully designed
optimum guardingand performance.
=
-.-" ":;
E o.or :-...'''."' :.::-"'; _'i"-t:tt, '':'--
l-;:-:--
---
;
be
- t -.-
- -
..-..-.- -
-.1
I
--!---
r-+-:
;:
-,--i-
---';a-
%LSB 12 B|TS
@
13
14
F
GUARD OIL
FOR0V ro +5V
DACCONNECTED
- --.1
;;^-^-
u
s
15
0.fi)'l
z
f
F
U
16
1?
%LSB r8 B|TS
@
FOROVTO +IOV
DACCONNECTED
10ps
1009s
SETTLING IME
T
lms
for
Settling Time (Voltage auQuil vs.o/o'of-Full-Scale-Error
LSB Steps (Essentiallylndependent of Amplifier Used). With
Degtitcher I V, the LSB Step at the Maior Carry Settlesas
Fastas the Typical LSB Step, Following the | | W Hold
Period.
l o l O
, Issr 6s
t
DAC CONNECTED FOR !5V
O
53
t
O
s2
O
49
:
O
48
o I
47 |
l
DAC CONNECT€D FOR IlOV
Figure 3. Output Voltage Connections and SuggestedPCB
Guarding (Unipolar and Biqolar)
TNOTE: All curves tyPical at rated supply voltage.
F.S. = Full Scale
-L
GAIN AND OFFSET ADJUSTMENTS
The gain and offset adjustments are made with external
potentiometers which the user supplies. With the appropriate
digital inputs applied, these potentiometers are adjusted until
the desired output voltage is obtained. The proper connec-
tions for offset and gain are shown in Figure 4. The volt-
meter used to measure the output should be capable of stable
resolution of 1/4LSB in the region of zero and full scale.
Because of the interaction berween offset and gain adjust-
ments, the adjustment procedure described below should be
carefully followed. Offset adjustment affects gain, but gain
adjustment does not affect offset.
1 1 3 6 = S H O R Tl 3 5 = O P E N
l
cvv 1 1 3 8 = 3 3 0 k 1 1 3 8 =1 5 0 k
100k
20f
OFFSET
ADJUST
100k
1136=56Ok
1138= M
2
cw
erpoLa;-
2M
OFFSET
TO PIN 34
OR PIN 69
100k
207
GAIN
ADJUST
DIFFERENTIAL LIN EARITY ADJ USTMENT
EachDAC1136l1138has beenfactory calibrated
and
testedto achieve performance
the
indicatedin the electrical
specifications.
Beforeattempringrecalibration, is imperative
it
that the circuit be checkedto confirm that all previouslyde-
scribed
precautions
havebeentakento insure
properapplica-
tion at the 16-or 18-birlevel.Basically, DAC is trimmed
the
by comparinga bit to the sum of all lower bits, and adjusting,
if necessary, a one LSB positivedifference.
for
The top 4
major carries, MSB minusthe sum of bits 2-through-the-
i.e.,
LSB, down through bit 4 minus the sum of bits 5-through-the-
LSB,can be trimmedusingthe procedure
outlinedbelow.A
differentialvoltmeter capable 1OOtrrV Scaleshouldbe
of
Full
connected V9g1 of the DAC. This will resolve LSB
to
an
which at 18 bits is 38pV (10V range). Fluke 895,4, equiv-
A
or
alentis recommended.
1. Bit 4 Trim
a . S e tb i t i n p u t st o 1 1 1 1 0 . . . . O .
b. Readthe output voltageby nulling rhe voltmeter.
c . S e tb i t i n p u t st o 1 1 1 0 1. . . . 1 .
d. Readvoltageby nulling voltmeter. This readingshould
be equalto that of step 1b plus 1LSB.Adjust bit 4 if
(see
required
84, Figure6).
2. Bit 3 Trim
a . S e tb i t i n p u t st o 1 1 1 0 . . . . O .
b. Readoutput voltageby nulling the voltmeter.
c. Setinputsto 1101 . . . . 1.
d. Readvoltageby nulling the voltmeter.This reading
shouldbe equalto that of step2b plus 1LSB.Adjust
(see83, Figure6).
bit 3 if required
3. Bit 2 Trim
a. Setbit inputsto 110 . . . . 0.
b. Readoutput voltageby nulling the voltmerer.
c. Setbit inputsto 101 . . . . 1.
d. Readvoltageby nulling vokmeter. This readingshould
be equalto that of step 3b plus lLSB. Adjust bit 2
(see82, Figure6),
if required
4. Bit 1 (MSB) Trim
a. Set bit switches 100 . . . . O.
to
b. Readoutput voltageby nulling the voltmeter.
c. Setbit switches 011 . . . . 1.
to
d. Readvoltageby nulling voltmerer.This readingshould
be equalto that of step4b plus 1LSB.Adjust bit 1
(MSB)if required
(see
MSB,Figure6).
If insufficientrangeexistson any adjustment,then a separate
(see
adjustrnent the rygightof bits 5-through-the-LSB
for
-+ LSB, Figure6) shouldbe performeil.This condition
Sum B5
will probably not occur on bit 2, 3 and 4 but might occur on
the MSB.If adjusfinent the sum of bits 5-through-the-LSB
of
is
made,the trim procedurefor all bits shouldbe repeated.
Ob-
viously, sincethe procedureaffectsthe weight of individual
bits, it affectsthe overallgain of the DAC. The final step
shouldbe adjustmentof gain (usersuppliedadjustmentex-
ternalto module,or pot at edgeof mountingcard).
2M
tN753A
L
r
r
-
l
T-
1,",*o
3.01k
1%
50mW
t
0
69
0
46
6 (
4 9 4
3.01k
1%
50mW
DACl 136
DAcl138
"^l
-15vdc coMMoN
+lsvdc
NorEs:
1. ALL FIXEDRESISTORS 5%CARBON
ARE
COMP,
UNLESS
OTHERWISE
NOTED.
2 . A L L P O T E N T I O M E T E R S 2 O . T U R I N F I N I T E E S O L U T T OY P E .
ARE
N
R
TN
Figure 4. Gain and Offset Adjustments
For unipolarmode, apply a digital input of all "1's" (com-
plementarybinary code for zero ourpur) and adjustthe offset
potentiometeruntil a 0.00000V ourput is obtained (see
Table I). Once the appropriate
offset adjustmenrhasbeen
made,apply a digital input of all "0's". Adjust the gain
potentiometeruntil the plus full scale
output is obtained
(see
TableI).
For bipolarmode,apply a digitalinput of all "L's" (comple-
mentary offset binary codefor minus full scale)and adjustthe
offset potentiometerfor the proper minus full scaleoutput
voltage(seeTable I). Oncethe appropriate
minus full scale
adjustmenthasbeenmade,apply a digital input of all "0's".
Adjust the gain potentiometeruntil the plus full scaleoutpur
shownbelowis obtained.
RANGE
IDEAL OUTPUT
*'--:-.'
All 11...1
l DACl138 ; DAC1136
i
All 00...0
:+9.999962V +9.999848V
:+4.99998IY +4.999924V
l
Unipolar:
i
OV++lOV
OV--++5V
Bipolar:
-1OV--r+10V
-5V -+ +5V
-
0.ooooov
0.00000v
-lo.ooooov
+9.999695v
l+9.999934Y
-5.ooo0ov i+4.999962Y
++.9998+8v
i
-
To adjust,
iAdjust ZERO potl
Adjust GAIN pot
Table l. Full Sale Output
.L
Test/Measurement
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