a
Digital PAL/NTSC Video Encoder with 10-Bit
SSAF™ and Advanced Power Management
ADV7170/ADV7171*
Programmable Chroma Filters (Low-Pass [0.65 MHz,
FEATURES
1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
Programmable VBI (Vertical Blanking Interval)
High Quality 10-Bit Video DACs
Programmable Subcarrier Frequency and Phase
SSAF (Super Sub-Alias Filter)
Programmable LUMA Delay
Advanced Power Management Features
Individual ON/OFF Control of Each DAC
CGMS (Copy Generation Management System)
CCIR and Square Pixel Operation
WSS (Wide Screen Signalling)
Integrated Subcarrier Locking to External Video Source
Simultaneous Y, U, V, C Output Format
Color Signal Control/Burst Signal Control
NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60
Interlaced/Noninterlaced Operation
Single 27 MHz Clock Required ( 2 Oversampling)
Complete On-Chip Video Timing Generator
80 dB Video SNR
Programmable Multimode Master/Slave Operation
32-Bit Direct Digital Synthesizer for Color Subcarrier
Macrovision AntiTaping Rev 7.01 (ADV7170 Only)**
Multistandard Video Output Support:
Closed Captioning Support
Composite (CVBS)
Teletext Insertion Port (PAL-WST)
Component S-Video (Y/C)
On-Board Color Bar Generation
Component YUV and RGB
On-Board Voltage Reference
EuroSCART Output (RGB + CVBS/LUMA)
2-Wire Serial MPU Interface (I
2
C
®
Compatible and Fast I
2
C)
Component YUV + CHROMA
Single Supply +5 V or +3.3 V Operation
Video Input Data Port Supports:
Small 44-Lead PQFP/TQFP Packages
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
APPLICATIONS
SMPTE 170M NTSC-Compatible Composite Video
High Performance DVD Playback Systems, Portable
ITU-R BT.470 PAL-Compatible Composite Video
Video Equipment Including Digital Still Cameras and
Programmable Simultaneous Composite
Laptop PCs, Video Games, PC Video/Multimedia and
and S-Video or RGB (SCART)/YUV Video Outputs
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)
Programmable Luma Filters (Low-Pass [PAL/NTSC])
Notch, Extended (SSAF, CIF and QCIF)
FUNCTIONAL BLOCK DIAGRAM
TTXREQ
TTX
M
U 10
L
T
I 10
P
L
E
10
X
E
R
V
AA
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
10
CGMS & WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
YUV TO
RBG
MATRIX
10
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
DAC D (PIN 27)
DAC C (PIN 26)
RESET
COLOR
DATA
P7–P0
P15–P8
8
4:2:2 TO
4:4:4
8
INTER-
POLATOR
8
Y 8
YCrCb
TO
U
YUV
MATRIX
V
9
9
PROGRAMMABLE
LUMINANCE
FILTER
10
PROGRAMMABLE
CHROMINANCE 10
FILTER
10
VIDEO TIMING
GENERATOR
I
2
C MPU PORT
REAL-TIME
CONTROL
CIRCUIT
U
10
10
DAC B (PIN 31)
ADD
SYNC
INTER-
POLATOR
8
8
8
ADD
BURST 8
8
INTER-
POLATOR 8
10
V
10-BIT
DAC
DAC A (PIN 32)
HSYNC
FIELD/VSYNC
BLANK
10
ADV7170/ADV7171
VOLTAGE
REFERENCE
CIRCUIT
V
REF
R
SET
COMP
SIN/COS
DDS BLOCK
CLOCK
SCLOCK
SDATA
ALSB
SCRESET/RTC
GND
*Protected
by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This
device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
SSAF is a trademark of Analog Devices, Inc.
I
2
C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADV7170/ADV7171–SPECIFICATIONS
5 V SPECIFICATIONS
(V
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS
Output Current
3
Output Current
4
DAC-to-DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
VOLTAGE REFERENCE
Reference Range, V
REF
POWER REQUIREMENTS
5
V
AA
Normal Power Mode
I
DAC
(max)
6
I
DAC
(min)
6
I
CCT7
Low Power Mode
I
DAC
(max)
6
I
DAC
(min)
6
I
CCT7
Sleep Mode
I
DAC8
I
CCT9
Power Supply Rejection Ratio
AA
=
+5 V
5%
1
, V
REF
= 1.235 V, R
SET
= 150
Conditions
1
. All specifications T
MIN
to T
MAX2
unless otherwise noted.)
Min
Typ
Max
10
Units
Bits
LSB
LSB
V
V
µA
pF
V
V
µA
pF
mA
mA
%
V
kΩ
pF
V
V
mA
mA
mA
mA
mA
mA
µA
µA
%/%
R
SET
= 300
Ω
Guaranteed Monotonic
2
V
IN
= 0.4 V or 2.4 V
±
0.6
±
1
0.8
±
1
10
I
SOURCE
= 400
µA
I
SINK
= 3.2 mA
2.4
0.4
10
10
R
SET
= 150
Ω,
R
L
= 37.5
Ω
R
SET
= 1041
Ω,
R
L
= 262.5
Ω
33
34.7
5
1.5
30
37
0
I
OUT
= 0 mA
I
VREFOUT
= 20
µA
1.142
4.75
R
SET
= 150
Ω,
R
L
= 37.5
Ω
R
SET
= 1041
Ω,
R
L
= 262.5
Ω
1.235
5.0
150
20
75
80
20
75
0.1
0.001
0.01
+1.4
30
1.327
5.25
155
90
90
COMP = 0.1
µF
0.5
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T
MIN
to T
MAX
: 0°C to +70°C.
3
Full drive into 37.5
Ω
doubly terminated load.
4
Minimum drive current (used with buffered/scaled output load).
5
Power measurements are taken with Clock Frequency = 27 MHz. Max T
J
= 110°C.
6
I
DAC
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces I
DAC
correspondingly.
7
I
CCT
(Circuit Current) is the continuous current required to drive the device.
8
Total DAC current in Sleep Mode.
9
Total continuous current during Sleep Mode.
Specifications subject to change without notice.
–2–
REV. 0
ADV7170/ADV7171
3.3 V SPECIFICATIONS
(V
Parameter
STATIC PERFORMANCE
3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
3
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN3, 4
Input Capacitance, C
IN
DIGITAL OUTPUTS
3
Output High Voltage, V
OH
Output Low Voltage, V
OL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS
3
Output Current
4, 5
Output Current
6
DAC-to-DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
POWER REQUIREMENTS
3, 7
V
AA
Normal Power Mode
I
DAC
(max)
8
I
DAC
(min)
8
I
CCT9
Low Power Mode
I
DAC
(max)
8
I
DAC
(min)
8
I
CCT9
Sleep Mode
I
DAC10
I
CCT11
Power Supply Rejection Ratio
AA
=
+3.0 V – 3.6 V
1
, V
REF
= 1.235 V, R
SET
= 150
Conditions
1
. All specifications T
MIN
to T
MAX2
unless otherwise noted.)
Min
Typ
Max
10
Units
Bits
LSB
LSB
V
V
µA
pF
V
V
µA
pF
mA
mA
%
V
kΩ
pF
V
mA
mA
mA
mA
mA
mA
µA
µA
%/%
R
SET
= 300
Ω
Guaranteed Monotonic
2
V
IN
= 0.4 V or 2.4 V
±
0.6
±
1
0.8
±
1
10
I
SOURCE
= 400
µA
I
SINK
= 3.2 mA
2.4
0.4
10
10
R
SET
= 150
Ω,
R
L
= 37.5
Ω
R
SET
= 1041
Ω,
R
L
= 262.5
Ω
33
34.7
5
2.0
30
37
0
I
OUT
= 0 mA
3.0
R
SET
= 150
Ω,
R
L
= 37.5
Ω
R
SET
= 1041
Ω,
R
L
= 262.5
Ω
3.3
150
20
35
80
20
35
0.1
0.001
0.01
+1.4
30
3.6
155
COMP = 0.1
µF
0.5
NOTES
11
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
12
Temperature range T
MIN
to T
MAX
: 0°C to +70°C.
13
Guaranteed by characterization.
14
Full drive into 37.5
Ω
load.
15
DACs can output 35 mA typically at 3.3 V (R
SET
= 150
Ω
and R
L
= 37.5
Ω),
optimum performance obtained at 18 mA DAC current (R
SET
= 300
Ω
and R
L
= 75
Ω).
16
Minimum drive current (used with buffered/scaled output load).
17
Power measurements are taken with Clock Frequency = 27 MHz. Max T
J
= 110°C.
18
I
DAC
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces I
DAC
correspondingly.
19
I
CCT
(Circuit Current) is the continuous current required to drive the device.
10
Total DAC current in Sleep Mode.
11
Total continuous current during Sleep Mode.
Specifications subject to change without notice.
REV. 0
–3–
ADV7170/ADV7171–SPECIFICATIONS
5 V DYNAMIC SPECIFICATIONS
Parameter
Differential Gain
3, 4
Differential Phase
3, 4
Differential Gain
3, 4
Differential Phase
3, 4
SNR
3, 4
(Pedestal)
SNR
3, 4
(Pedestal)
SNR
3, 4
(Ramp)
SNR
3, 4
(Ramp)
Hue Accuracy
3, 4
Color Saturation Accuracy
3, 4
Chroma Nonlinear Gain
3, 4
Chroma Nonlinear Phase
3, 4
Chroma/Luma Intermod
3, 4
Chroma/Luma Gain Inequality
3, 4
Chroma/Luma Delay Inequality
3, 4
Luminance Nonlinearity
3, 4
Chroma AM Noise
3, 4
Chroma PM Noise
3, 4
(V
AA
= +5 V 5%
1
, V
REF
= 1.235 V, R
SET
= 150
otherwise noted.)
Min
. All specifications T
MIN
to T
MAX2
unless
Typ
0.3
0.4
1.0
1.0
80
70
60
58
0.7
0.9
0.6
0.3
0.2
1.0
0.5
0.8
85
81
Max
0.7
0.7
2.0
2.0
Units
%
Degrees
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±
%
±
Degrees
±
%
±
%
ns
±
%
dB
dB
Conditions
1
Normal Power Mode
Normal Power Mode
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
RMS
Peak Periodic
1.2
1.4
0.5
0.4
1.4
2.0
1.4
Referenced to 40 IRE
82
79
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T
MIN
to T
MAX
: 0°C to +70°C.
3
Guaranteed by characterization.
4
The low pass filter only and guaranteed by design.
Specifications subject to change without notice.
3.3 V DYNAMIC SPECIFICATIONS
Parameter
Differential Gain
3
Differential Phase
3
Differential Gain
3
Differential Phase
3
SNR
3
(Pedestal)
SNR
3
(Pedestal)
SNR
3
(Ramp)
SNR
3
(Ramp)
Hue Accuracy
3
Color Saturation Accuracy
3
Luminance Nonlinearity
3, 4
Chroma AM Noise
3, 4
Chroma PM Noise
3, 4
Chroma Nonlinear Gain
3, 4
Chroma Nonlinear Phase
3, 4
Chroma/Luma Intermod
3, 4
(V
AA
= +3.0 V – 3.6 V
1
, V
REF
= 1.235 V, R
SET
= 150
otherwise noted.)
Min
1.0
0.5
0.6
0.5
78
70
60
58
1.0
1.0
1.4
80
79
0.6
0.3
0.2
. All specifications T
MIN
to T
MAX2
unless
Max
Units
%
Degrees
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±
%
dB
dB
±
%
±
Degrees
±
%
Conditions
1
Normal Power Mode
Normal Power Mode
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
RMS
Peak Periodic
Typ
Referenced to 40 IRE
0.5
0.4
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T
MIN
to T
MAX
: 0°C to +70°C.
3
Guaranteed by characterization.
4
These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
Specifications subject to change without notice.
–4–
REV. 0
ADV7170/ADV7171
5 V TIMING SPECIFICATIONS
Parameter
MPU PORT
3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
ANALOG OUTPUTS
3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND
PIXEL PORT
5, 6
f
CLOCK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Control Setup Time, t
11
Control Hold Time, t
12
Digital Output Access Time, t
13
Digital Output Hold Time, t
144
Pipeline Delay, t
15 4
TELETEXT
3, 4, 7
Digital Output Access Time, t
16
Data Setup Time, t
17
Data Hold Time, t
18
RESET CONTROL
3, 4
RESET
Low Time
6
(V
AA
= 4.75 V – 5.25 V
1
, V
REF
= 1.235 V, R
SET
= 150
otherwise noted.)
. All specifications T
MIN
to T
MAX2
unless
Min
0
0.6
1.3
0.6
0.6
100
Typ
Max
400
Units
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
Conditions
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
300
300
0.6
7
0
27
8
8
3.5
4
4
3
11
8
48
20
2
6
16
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
ns
ns
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.
2
Temperature range T
MIN
to T
MAX
: 0
o
C to +70
o
C.
3
TTL input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load
≤
10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC,
FIELD/VSYNC,
BLANK
Clock Input:
CLOCK
7
Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
REV. 0
–5–
Embedded System
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