a
FEATURES
AD9891: 10-Bit 20 MHz Version
AD9895: 12-Bit 30 MHz Version
Correlated Double Sampler (CDS)
4 6 dB Pixel Gain Amplifier (
PxGA
®
)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 20 MHz A/D Converter (AD9891)
12-Bit 30 MHz A/D Converter (AD9895)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing
Core with 1 ns Resolution
On-Chip 5 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
4-Phase Vertical Transfer Clocks
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Option
64-Lead CSPBGA Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
CCD Signal Processors with
Precision Timing
™
Generator
AD9891/AD9895
PRODUCT DESCRIPTION
The AD9891 and AD9895 are highly integrated CCD signal
processors for digital still camera applications. Both include a
complete analog front end with A/D conversion combined with
a full-function programmable timing generator. A
Precision
Timing
core allows adjustment of high speed clocks with 1 ns
resolution at 20 MHz operation and 700 ps resolution at 30
MHz operation.
The AD9891 is specified at pixel rates of up to 20 MHz, and
the AD9895 is specified at 30 MHz. The analog front end
includes black level clamping, CDS,
PxGA,
VGA, and a 10-Bit
or 12-Bit A/D converter. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 64-lead CSPBGA, the AD9891 and
AD9895 are specified over an operating temperature range of
–20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VRT
VRB
AD9891/AD9895
4dB
CCDIN
CDS
6dB
2dB TO 36dB
VREF
PxGA
VGA
ADC
10 OR 12
DOUT
CLAMP
INTERNAL CLOCKS
CLAMP
DCLK
CLPOB/PBLK
RG
4
H1–H4
4
V1–V4
8
VSG1–VSG8
V-H
CONTROL
HORIZONTAL
DRIVERS
PRECISION
TIMING
GENERATOR
FD/LD
MSHUT
STROBE
CLO
SYNC
GENERATOR
INTERNAL
REGISTERS
VSUB SUBCK
HD
VD SYNC
CLI
SL
SCK DATA
PxGA
is a registered trademark and
Precision Timing
is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9891/AD9895
TABLE OF CONTENTS
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 3
AD9891 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 4
AD9895 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 6
PACKAGE THERMAL CHARACTERISTICS . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATION-AD9891 . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS-AD9891 . . . . . . . . . . . 7
PIN CONFIGURATION-AD9895 . . . . . . . . . . . . . . . . . . . 8
PIN FUNCTION DESCRIPTIONS-AD9895 . . . . . . . . . . . 8
SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . . 9
EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . 9
TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10
SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical System Block Diagram . . . . . . . . . . . . . . . . . . . . 11
PRECISION TIMING HIGH SPEED TIMING
GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
High Speed Clock Programmability . . . . . . . . . . . . . . . . . .12
H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . .13
Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
HORIZONTAL CLAMPING AND BLANKING . . . . . . . . 15
Individual CLPOB, CLPDM, and PBLK Sequences . . . . . 15
Individual HBLK Sequences . . . . . . . . . . . . . . . . . . . . . . .15
Horizontal Sequence Control . . . . . . . . . . . . . . . . . . . . . . .15
VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . .17
Individual Vertical Sequences . . . . . . . . . . . . . . . . . . . . . .18
Individual Vertical Regions . . . . . . . . . . . . . . . . . . . . . . . .19
Complete Field: Combining the Regions . . . . . . . . . . . . . . 20
Vertical Sequence Alteration . . . . . . . . . . . . . . . . . . . . . . .21
Second Vertical Sequence During VSG Lines . . . . . . . . . . 22
Vertical Sweep Mode Operation . . . . . . . . . . . . . . . . . . . .22
Vertical Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . .24
Frame Transfer CCD Mode . . . . . . . . . . . . . . . . . . . . . . 24
Vertical Sensor Gate (Shift Gate) Timing . . . . . . . . . . . . .25
SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . .26
Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . .26
Low Speed Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . .26
SUBCK Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Readout After Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . .27
VSUB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MSHUT and STROBE Control . . . . . . . . . . . . . . . . . . . .27
Example of Exposure and Readout of Interlaced Frame . . .29
ANALOG FRONT END DESCRIPTION AND
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 30
Input Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PxGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
PxGA
Color Steering Mode Timing . . . . . . . . . . . . . . . . 31
Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PxGA
and VGA Gain Curves . . . . . . . . . . . . . . . . . . . . . 33
Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
POWER-UP AND SYNCHRONIZATION . . . . . . . . . . . . 34
Recommended Power-Up Sequence for Master Mode . . . .34
SYNC During Master Mode Operation . . . . . . . . . . . . . . .35
Synchronization in Slave Mode . . . . . . . . . . . . . . . . . . . . .35
POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . 35
HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . 37
VERTICAL TIMING EXAMPLE . . . . . . . . . . . . . . . . . . . 39
CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . .40
SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . .41
Notes About Accessing a Double-Wide Register . . . . . . . 41
NOTES ON REGISTER LISTING . . . . . . . . . . . . . . . . . . 42
COMPLETE REGISTER LISTING . . . . . . . . . . . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 57
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
–2–
REV. A
AD9891/AD9895–SPECIFICATIONS
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
AVDD1, AVDD2 (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1–H4 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
POWER DISSIPATION–AD9891 (See TPC 1 for Power Curves)
20 MHz, Typ Supply Levels, 100 pF H1–H4 Loading
Power from HVDD Only
*
Power-Down 1 Mode
Power-Down 2 Mode
Power-Down 3 Mode
POWER DISSIPATION–AD9895 (See TPC 4 for Power Curves)
30 MHz, Typ Supply Levels, 100 pF H1–H4 Loading
Power from HVDD Only
*
Power-Down 1 Mode
Power-Down 2 Mode
Power-Down 3 Mode
MAXIMUM CLOCK RATE (CLI)
AD9891
AD9895
*
Min
–20
–65
2.7
2.7
3.0
3.0
2.7
2.7
Typ
Max
+85
+150
Unit
°C
°C
V
V
V
V
V
V
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
MHz
MHz
3.0
3.0
5.0
5.0
3.0
3.0
380
220
42
8
2.5
600
320
138
22
2.5
3.6
3.6
5.25
5.25
3.6
3.6
20
30
Pixel Frequency]
HVDD
Number of H-Outputs Used
The total power dissipated by the HVDD supply may be approximated using the equation:
Total HVDD Power
= [C
LOAD
HVDD
Reducing the H-loading, using only two of the outputs, and/or using a lower
HVDD
supply will reduce the power dissipation.
Actual HVDD power may be slightly higher than the calculated value because of stray capacitance inherent in the PCB layout/routing.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
(RGVDD = HVDD = 4.75 V to 5.25 V, DVDD = DRVDD = 2.7 V to 3.5 V, C
L
= 20 pF, T
MIN
to T
MAX
,
unless otherwise noted.)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
V
OH
V
OL
Min
2.1
0.6
10
10
10
2.2
0.5
VDD – 0.5
0.5
24
100
Typ
Max
Unit
V
V
µA
µA
pF
V
V
V
V
mA
pF
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ I
OH
= 2 mA
Low Level Output Voltage @ I
OL
= 2 mA
RG and H-DRIVER OUTPUTS (H1–H4)
High Level Output Voltage @ Max Current
Low Level Output Voltage @ Max Current
Maximum Output Current (Programmable)
Maximum Load Capacitance (for Each Output)
Specifications subject to change without notice.
REV. A
–3–
AD9891/AD9895
AD9891–ANALOG SPECIFICATIONS
Parameter
CDS
Gain
Allowable CCD Reset Transient
Max Input Range before Saturation
Max CCD Black Pixel Amplitude
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (PxGA Code 32)
Med Gain (PxGA Code 0)
Max Gain (PxGA Code 31)
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Code 70)
Max Gain (VGA Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 70)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
*
(AVDD1, AVDD2 = 3.0 V, f
CLI
= 20 MHz, T
MIN
to T
MAX
, unless otherwise noted.)
Typ
0
500
Min
Max
Unit
dB
mV
V p-p
mV
V p-p
V p-p
Steps
Notes
Input signal characteristics*
1.0
±
200
1.0
1.6
64
Guaranteed
–2.5
+3.5
+9.5
1.6
2.0
1024
Guaranteed
2
36
256
0
63.75
10
±
0.4
Guaranteed
2.0
2.0
1.0
±
1.0
dB
dB
dB
V p-p
V p-p
Steps
Default setting
dB
dB
Steps
Measured at ADC output
LSB
LSB
Bits
LSB
V
V
V
Includes entire signal chain
Includes 4 dB default
PxGA
gain
Gain = (0.035 Code) + 3.55 dB
12 dB gain applied
AC grounded input, 6 dB gain applied
Measured with step change on supply
5
38.5
6
39.5
0.2
0.6
40
7
40.5
dB
dB
%
LSB rms
dB
Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
200mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
Specifications subject to change without notice.
–4–
REV. A
AD9891/AD9895
AD9895–ANALOG SPECIFICATIONS
Parameter
CDS
Gain
Allowable CCD Reset Transient
Max Input Range before Saturation
Max CCD Black Pixel Amplitude
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (PxGA Code 32)
Med Gain (PxGA Code 0)
Max Gain (PxGA Code 31)
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Code 70)
Max Gain (VGA Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 70)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
*
(AVDD1, AVDD2 = 3.0 V, f
CLI
= 30 MHz, T
MIN
to T
MAX
, unless otherwise noted.)
Typ
0
500
Min
Max
Unit
dB
mV
V p-p
mV
V p-p
V p-p
Steps
Notes
Input signal characteristics*
1.0
±
200
1.0
1.6
64
Guaranteed
–2.5
+3.5
+9.5
1.6
2.0
1024
Guaranteed
2
36
256
0
255
12
±
0.5
Guaranteed
2.0
2.0
1.0
±
1.0
dB
dB
dB
V p-p
V p-p
Steps
Default setting
dB
dB
Steps
Measured at ADC output
LSB
LSB
Bits
LSB
V
V
V
Includes entire signal chain
Includes 4 dB default
PxGA
gain
Gain = (0.035 Code) + 3.55 dB
12 dB gain applied
AC grounded input, 6 dB gain applied
Measured with step change on supply
5
38.5
6
39.5
0.2
0.8
40
7
40.5
dB
dB
%
LSB rms
dB
Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
200mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
Specifications subject to change without notice.
REV. A
–5–
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