a
FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Complies with VRM 9.0 and Intel VR Down Guideline
with Lowest System Cost
Digitally Selectable 2- or 3-Phase Operation
at up to 500 kHz per Phase
Quad Logic-level PWM Outputs for Interface to
External High-Power Drivers
Active Current Balancing between All Output Phases
Accurate Multiple VRM Module Current Sharing
5-Bit Digitally Programmable 1.1 V to 1.85 V Output
Total Output Accuracy 0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Enhanced Power Good Output Detects Open Outputs in
Multi-VRM Power Systems
Overvoltage Protection Crowbar Protects Microprocessors
with No Additional External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Pentium
®
4 Processors
AMD Athlon Processors
VRM Modules
5-Bit Programmable 2-/3-Phase
Synchronous Buck Controller
ADP3163
FUNCTIONAL BLOCK DIAGRAM
VCC
PC
ADP3163
UVLO
& BIAS
SET
RESET
CROWBAR
REF
GND
3.0V
REFERENCE
DAC+20%
2-/3-PHASE
DRIVER
LOGIC
PWM1
PWM2
PWM3
PGND
CT
OSCILLATOR
POWER
GOOD
PWRGD
SHARE
CMP
DAC+20%
CS–
CMP
CS+
FB
COMP
SOFT
START
g
m
VID
DAC
VID4 VID3 VID2 VID1 VID0
GENERAL DESCRIPTION
The ADP3163 is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 5 V or
12 V main supply into the core supply voltage required by high
performance Intel processors. The ADP3163 uses an internal
5-bit DAC to read a voltage identification (VID) code directly
from the processor, which is used to set the output voltage between
1.1 V and 1.85 V. The ADP3163 uses a current mode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2- or 3-phase operation, allowing for
the construction of up to three complementary buck switching
stages. These stages share the dc output current to reduce
overall output voltage ripple. An active current balancing func-
tion ensures that all phases carry equal portions of the total load
current, even under large transient loads, to minimize the size of
the inductors.
The ADP3163 also uses a unique supplemental regulation tech-
nique called active voltage positioning (ADOPT) to enhance
load transient performance. Active voltage positioning results in
a dc/dc converter that meets the stringent output voltage specifi-
cations for high performance processors, with the minimum
number of output capacitors and smallest footprint. Unlike
voltage-mode and standard current-mode architectures, active
voltage positioning adjusts the output voltage as a function of
the load current so that it is always optimally positioned for a
system transient. The ADP3163 also provides accurate and
reliable short circuit protection, adjustable current limiting, and
an enhanced Power Good output that can detect open outputs
in any phase for single or multi-VRM systems.
The ADP3163 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 20-lead TSSOP package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADP3163–SPECIFICATIONS
1
(VCC = 12 V, I
Parameter
FEEDBACK INPUT
Accuracy
1.1 V Output
1.6 V Output
1.85 V Output
Line Regulation
Input Bias Current
Crowbar Trip Point
Crowbar Reset Point
Crowbar Response Time
REFERENCE
Output Voltage
Output Current
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
Pull-Up Resistance
Internal Pull-Up Voltage
OSCILLATOR
Maximum Frequency
2
Frequency Variation
Symbol
V
FB
Conditions
REF
= 150 A, T
A
= 0 C to 70 C, unless otherwise noted.)
Min
Typ
Max
Unit
∆V
FB
I
FB
V
CROWBAR
t
CROWBAR
V
REF
I
REF
V
IL(VID)
V
IH(VID)
I
VID
R
VID
1.091
1.587
1.835
VCC = 10 V to 14 V
% of Nominal Output
% of Nominal Output
Overvoltage to PWM Going Low
115
40
1.1
1.6
1.85
0.01
5
120
50
400
3.00
1.109
1.613
1.865
50
125
60
V
V
V
%
nA
%
%
ns
V
µA
V
V
µA
kΩ
V
kHz
kHz
kHz
kHz
µA
µA
MΩ
mmho
µA
V
mV
kHz
mV
mV
mV
µA
ns
2.952
300
3.048
0.8
2.0
VID(X) = 0 V
33
2.7
3000
475
850
1100
260
40
70
43
3.0
90
3.3
f
CT(MAX)
f
CT
I
CT
CT Charge Current
ERROR AMPLIFIER
Output Resistance
Transconductance
Output Current
Maximum Output Voltage
Output Disable Threshold
–3 dB Bandwidth
CURRENT SENSE
Threshold Voltage
T
A
= 25°C, CT = 150 pF
T
A
= 25°C, CT = 68 pF
T
A
= 25°C, CT = 47 pF
T
A
= 25°C, V
FB
in Regulation
T
A
= 25°C, V
FB
= 0 V
575
1000
1300
300
65
1
2.2
575
3.0
800
500
158
92
0
1
50
675
1250
1500
340
80
R
O(ERR)
g
m(ERR)
I
O(ERR)
V
COMP(MAX)
V
COMP(OFF)
BW
ERR
V
CS(TH)
2.0
FB Forced to 0 V
FB Forced to V
OUT
– 3%
COMP = Open
CS+ = VCC,
FB Forced to V
OUT
– 3%
FB
≤
750 mV
0.8 V
≤
SHARE
≤
1 V
CS+ = CS– = VCC
CS+ – (CS–)
≥
173 mV
143
80
2.45
875
173
108
5
5
Input Bias Current
Response Time
to PWM Going Low
CURRENT SHARING
Output Source Current
Output Sink Current
Maximum Output Voltage
PHASE CONTROL
Input Low Voltage
Input High Voltage
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Voltage Low
Response Time
I
CS+
, I
CS–
t
CS
2
V
SHARE(MAX)
V
IL(PC)
V
IH(PC)
V
PWRGD(UV)
V
PWRGD(OV)
V
OL(PWRGD)
Percent of Nominal Output
Percent of Nominal Output
I
PWRGD(SINK)
= 1 mA
FB Forced to V
OUT
– 3%
300
3.0
400
mA
µA
V
V
V
%
%
mV
ns
0.8
2.0
75
115
80
120
375
250
85
125
525
–2–
REV. 0
ADP3163
Parameter
PWM OUTPUTS
Output Voltage Low
Output Voltage High
Duty Cycle Limit Per Phase
2
SUPPLY
DC Supply Current
Normal Mode
No CPU Mode
UVLO Mode
UVLO Threshold Voltage
UVLO Hysteresis
Symbol
V
OL(PWM)
V
OH(PWM)
DC
Conditions
I
PWM(SINK)
= 400
µA
I
PWM(SOURCE)
=400
µA
PC = GND
PC = REF
Min
Typ
100
5.0
Max
500
50
33
Unit
mV
V
%
%
4.0
I
CC
I
CC(NO CPU)
I
CC(UVLO)
V
UVLO
VID4 – VID0 = Open
VCC
≤
V
UVLO
, VCC Rising
5.9
0.5
3.75
3.5
350
6.4
0.8
5.5
5.5
500
6.9
1.0
mA
mA
µA
V
V
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
Guaranteed by design, not tested in production.
Specifications subject to change without notice.
PIN CONFIGURATION
RU-20
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
SHARE 6
COMP 7
GND 8
FB 9
CT 10
20 VCC
19 REF
18 PWM1
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC +0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This
is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
ADP3163
TOP VIEW
(NOT TO SCALE)
17 PWM2
16 PWM3
15 PC
14 PGND
13 CS–
12 CS+
11 PWRGD
ORDERING GUIDE
Model
ADP3163JRU
Temperature Range
0°C to 70°C
Package Description
Thin Shrink Small Outline
Package Option
RU-20 (TSSOP-20)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3163 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
ADP3163
PIN FUNCTION DESCRIPTIONS
Pin
1–5
Name
VID4 –
VID0
SHARE
Function
Voltage Identification DAC Inputs. These pins are pulled up to an internal 3 V reference, providing a
Logic 1 if left open. The DAC output programs the FB regulation voltage from 1.1 V to 1.85 V. Leaving all five
DAC inputs open results in the ADP3163 going into a “No CPU” mode, shutting off its PWM outputs.
Current Sharing Output. This pin is connected to the SHARE pins of other ADP3163s in multiple VRM sys-
tems to ensure proper current sharing between the converters. The voltage at this output programs the output
current control level between CS+ and CS–.
Error Amplifier Output and Compensation Point.
Ground. FB, REF and the VID DAC of the ADP3163 are referenced to this ground. This is a low current ground
that can also be used as a return for the FB pin in remote voltage sensing applications.
Feedback Input. Error amplifier input for remote sensing of the output voltage.
External capacitor CT connection to ground sets the frequency of the device.
Open drain output that signals when the output voltage is outside of the proper operating range or when a phase
is not supplying current even if the output voltage is in specification.
Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a volt-
age at this pin with respect to CS–.
Current Sense Negative Node. Negative input for the current comparator.
Power Ground. All internal biasing and logic output signals of the ADP3163 are referenced to this ground.
Phase Control Input. This logic-level input determines the number of active phases and the duty cycle limit of
each phase.
Logic-Level Output for the Phase 3 Driver.
Logic-Level Output for the Phase 2 Driver.
Logic-Level Output for the Phase 1 Driver.
3.0 V Reference Output.
Supply Voltage for the ADP3163.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
COMP
GND
FB
CT
PWRGD
CS+
CS–
PGND
PC
PWM3
PWM2
PWM1
REF
VCC
ADP3163
1 VID4
2 VID3
5-BIT CODE
3 VID2
4 VID1
5 VID0
6 SHARE
7 COMP
100
100nF
10 CT
PWRGD 11
8 GND
9 FB
VCC 20
REF 19
PWM1 18
PWM2 17
PWM3 16
PC 15
PGND 14
CS– 13
CS+ 12
20k
1 F
100nF
12V
Table I. PWM Outputs vs. Phase Control Code
PC
REF
GND
PWM3
ON
OFF
PWM2
ON
ON
PWM1
ON
ON
Maximum
Duty Cycle
33%
50%
V
FB
AD820
1.2V
Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit
–4–
REV. 0
Typical Performance Characteristics–ADP3163
10
4.5
4.4
SUPPLY CURRENT – mA
FREQUENCY – MHz
4.3
1.0
4.2
4.1
0.1
0
50
150
200
100
CT CAPACITANCE – pF
250
300
4.0
0
500
1500
2000
1000
OSCILLATOR FREQUENCY – kHz
2500
3000
TPC 1. Oscillator Frequency vs. Timing Capacitor (CT)
TPC 2. Supply Current vs. Oscillator Frequency
25
T
A
= 25 C
V
OUT
= 1.6V
20
NUMBER OF PARTS – %
15
10
5
0
–0.5
0
OUTPUT ACCURACY – % of Nominal
0.5
TPC 3. Output Accuracy Distribution
REV. 0
–5–
Analogue and Mixed Signal
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