(AVDD = 3 V 10%; DVDD = 3 V 10%; DGND = AGND = 0 V, f
DMCLK
=
16.384 MHz, f
SAMP
= 8 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Unit
Test Conditions/Comments
A, Y Versions
Min
Typ
Max
1.2
50
130
1.2
1
100
±
1.0
1.578
50
100
+1
–1
5
±
1.0
1.0
0.5
1.578
–2.85
1.0954
–6.02
1.32
1.08
1.32
V
ppm/°C 0.1
µF
Capacitor Required from
REFCAP to AGND2
Ω
V
Unloaded
kΩ
pF
mV
V
kΩ
pF
Max Output Swing = (1.578/1.2)
×
VREFCAP
f
C
= 32 kHz
Bits
%
µs
µs
V p-p
dBm
V p-p
dBm
+0.5
dB
dB
dB
dB
dB
–75
dB
dB
dBm0
dB
dB
dB
mV
dB
µs
kΩ
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
DAC Unloaded
Measured Differentially
Max Input = (1.578/1.2)
×
VREFCAP
Measured Differentially
–2.0
–0.7
±
0.1
78
79
77.5
–86
–61
–72
–107
–92
–93
0
–65
25
20
+1
–1
16
25
100
70
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to TPC 1.
300 Hz to 3400 Hz; f
SAMP
= 8 kHz, PUIA = 0
300 Hz to 3400 Hz; f
SAMP
= 8 kHz, PUIA = 1
0 Hz to f
SAMP
/2; f
SAMP
= 8 kHz
300 Hz to 3400 Hz; f
SAMP
= 8 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Input Amplifiers Bypassed
Total Harmonic Distortion
PGA = 0 dB
Intermodulation Distortion
Idle Channel Noise Crosstalk
ADC-to-DAC
ADC-to-ADC
DC Offset
Power Supply Rejection
Group Delay
4, 5
Input Resistance at PGA
2, 4, 6
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
–20
+20
Bits
µs
µs
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
–2–
REV. 0
AD73322L
Parameter
DAC SPECIFICATIONS
Maximum Voltage Output Swing
2
Single-Ended
Differential
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
Differential
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion) at 0 dBm0
PGA = 0 dB
Total Harmonic Distortion at 0 dBm0
PGA = 0 dB
Intermodulation Distortion
Idle Channel Noise Crosstalk
DAC-to-ADC
A, Y Versions
Min
Typ
Max
Unit
Test Conditions/Comments
DAC Unloaded
1.578
–2.85
3.156
3.17
1.0954
–6.02
2.1909
0
1.2
–0.6
+0.75
±
0.1
78.5
–89
–77
–81
–73
–75
V p-p
dBm
V p-p
dBm
V p-p
dBm
V p-p
dBm
V
dB
dB
dB
dB
dB
dBm0
dB
PGA = 6 dB
Max Output = (1.578/1.2)
×
VREFCAP
PGA = 6 dB
Max Output = 2
×
([1.578/1.2]
×
VREFCAP)
PGA = 6 dB
PGA = 6 dB
REFOUT Unloaded
1.0 kHz, 0 dBm0; Unloaded
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to TPC 2.
300 Hz to 3400 Hz; f
SAMP
= 8 kHz
300 Hz to 3400 Hz; f
SAMP
= 8 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0
Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
DAC1 Output Signal Level: AGND; DAC2
Output Signal Level: 1.0 kHz, 0 dBm0
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Interpolator Bypassed
–1.75
72
DAC-to-DAC
Power Supply Rejection
Group Delay
4, 5
Output DC Offset
2, 7
Minimum Load Resistance, R
L2, 8
Single-Ended
4
Differential
Maximum Load Capacitance, C
L2, 8
Single-Ended
Differential
FREQUENCY RESPONSE
(ADC and DAC)
9
Typical Output
Frequency (Normalized to FS)
0
0.03125
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
> 0.5
–50
–74
–102
–65
25
50
+5
150
150
500
100
dB
dB
dB
µs
µs
mV
Ω
Ω
pF
pF
+60
0
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
REV. 0
–3–
AD73322L
Parameter
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
IH
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUT
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
Three-State Leakage Current
POWER SUPPLIES
AVDD1, AVDD2
DVDD
I
DD10
Min
A, Y Versions
Typ
Max
DVDD
0.8
+10
10
DVDD
0.4
+10
3.3
3.3
Unit
V
V
µA
pF
V
V
µA
V
V
See Table I
|IOUT|
≤
100
µA
|IOUT|
≤
100
µA
Test Conditions/Comments
DVDD – 0.8
0
–10
DVDD – 0.4
0
–10
2.7
2.7
NOTES
1
Operating temperature range as follows: A Grade, T
MIN
= –40°C, T
MAX
= +85°C; Y Grade, T
MIN
= –40°C, T
MAX
= +105°C.
2
Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3
×
10
11
)/DMCLK.
7
Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.
8
At VOUT output.
9
Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB pream-
plifier bypassed and input gain of 0 dB.
10
Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = 3.3 V)
Conditions
ADCs On Only
DACs On Only
ADCs and DACs On
ADCs and DACs
and Input Amps On
ADCs and DACs
and AGT On
All Sections On
REFCAP On Only
REFCAP and
REFOUT On Only
All Sections Off
All Sections Off
Analog
Current
3.4
8.8
11.6
13.8
13.2
17.2
0.65
2.56
0
0
µA
Digital
Current
6.3
6.5
7.0
7.0
7.0
7.0
0
0
1.25
12.5
µA
Total Current
(Typ)
9.7
15.3
18.6
20.8
20.2
24.2
0.67
2.57
1.25
12.7
µA
Total Current
(Max)
12
20
23
26
26
31
1.25
4.5
1.8
40
µA
SE
1
1
1
1
1
1
0
0
0
0
MCLK
ON
Comments
YES
YES
YES
YES
YES
YES
NO
NO
YES
NO
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
MCLK Active Levels Equal to
0 V and DVDD
Digital Inputs Static and Equal
to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted.
京公网安备 11010802033920号
EEWORLD
