W24L257A
32K
×
8 HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L257A is a high-speed, low-power CMOS static RAM organized as 32768
×
8 bits that
operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
•
•
•
High-speed access time: 12/15/20 nS (max.)
Low-power consumption:
−
Active: 200 mW (typ.)
Single
+3.3V
power supply
Fully static operation
•
•
•
All inputs and outputs directly TTL compatible
Three-state outputs
Available packages: 28-pin 300 mil SOJ,
skinny DIP and standard type one TSOP
(8 mm
×
13.4 mm)
PIN CONFIGURATION
BLOCK DIAGRAM
V
DD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-DIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
WE
A13
A8
A9
A11
OE
V
SS
A0
.
.
A14
DECODER
CORE
ARRAY
ARRAY
CS
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
OE
WE
CONTROL
DATA I/O
I/O1
.
.
I/O8
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
A0−A14
I/O1−I/O8
CS
WE
OE
V
DD
V
SS
OE
A11
A9
A8
A13
WE
V
DD
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin
TSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
-1-
Publication Release Date: December 1996
Revision A5
W24L257A
TRUTH TABLE
CS
H
L
L
L
OE
X
H
L
X
WE
X
H
H
L
MODE
Not Selected
Output Disable
Read
Write
I/O1−I/O8
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB1
I
DD
I
DD
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
RATING
-0.5 to +4.6
-0.5 to V
DD
+0.5
1.0
-65 to +150
0 to +70
UNIT
V
V
W
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 3.3V
±
5%, V
SS
= 0V, Ta = 0 to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
Standby Power
Supply Current
SYM
.
V
IL
V
IH
I
LI
I
LO
V
OL
V
OH
I
DD
TEST CONDITIONS
-
-
V
IN
= V
SS
to V
DD
V
I/O
= V
SS
to V
DD,
CS = V
IH (min.)
or OE = V
IH (min.)
or WE = V
IL (max.)
I
OL
= +8.0 mA
I
OH
= -4.0 mA
12
CS = V
IL (max.),
I/O = 0 mA
Cycle = min.
Duty = 100%
15
20
MIN TYP
MAX.
.
.
-0.5
-
+0.8
+2.0
-
V
DD
+0.3
-10
-
+10
-10
-
2.4
-
-
-
-
-
-
-
-
-
-
-
-
-
+ 10
0.4
-
150
120
100
20
200
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
µA
I
SB
I
SB1
CS = V
IH (min.),
Cycle = min.
Duty = 100%
CS
≥
V
DD
-0.2V
Note: Typical characteristics are at V
DD
= 3.3V, Ta = 25° C.
-2-
W24L257A
CAPACITANCE
(V
DD
= 3.3V, Ta = 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
6
8
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0V to 3V
3 nS
1.5V
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
CONDITIONS
AC Test Loads and Waveform
R1 320 ohm
3.3V
OUTPUT
30 pF
Including
Jig and
Scope
R2
350 ohm
R1 320 ohm
3.3V
OUTPUT
5 pF
Including
Jig and
Scope
R2
350 ohm
(For T
CLZ
, T
OLZ
, T
CHZ
, T
OHZ
, T
WHZ
, T
OW
)
3.0V
90%
10%
3 nS
90%
10%
3 nS
0V
-3-
Publication Release Date: December 1996
Revision A5
W24L257A
AC Characteristics, continued
(V
DD
= 3.3V
±
5%, V
SS
= 0V, Ta = 0 to 70° C)
(1) Read Cycle
PARAMETER
SYM.
W24L257A-12
MIN.
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
T
RC
T
AA
T
ACS
T
AOE
T
CLZ
*
T
OLZ
*
T
CHZ
*
T
OHZ
*
T
OH
12
-
-
-
4
0
-
-
3
MAX.
-
12
12
6
-
-
6
6
-
W24L257A-15
MIN.
15
-
-
-
4
0
-
-
3
MAX.
-
15
15
8
-
-
7
7
-
W24L257A-20
MIN.
20
-
-
-
4
0
-
-
3
MAX.
-
20
20
10
-
-
10
10
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
∗These
parameters are sampled but not 100% tested
(2) Write Cycle
PARAMETER
SYM.
W24L257A-12
MIN.
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
CS
,
WE
W24L257A-15
MIN.
15
13
13
0
10
1
9
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
8
8
-
W24L257A-20
MIN.
20
17
17
0
12
1
10
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
10
10
-
UNIT
MAX.
-
-
-
-
-
-
-
-
7
7
-
T
WC
T
CW
T
AW
T
AS
T
WP
T
WR
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
12
10
10
0
10
1
7
0
-
-
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
∗These
parameters are sampled but not 100% tested
-4-
W24L257A
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
T
OH
D
OUT
T
AA
T
OH
Read Cycle 2
(Chip Select Controlled)
CS
T
ACS
D
OUT
T
CLZ
T
CHZ
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
OE
T
AOE
CS
T
OLZ
T
ACS
D
OUT
T
CLZ
T
CHZ
T
OHZ
T
OH
-5-
Publication Release Date: December 1996
Revision A5
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