W24L010A
128K
×
8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L010A is a high speed, low power CMOS static RAM organized as 131072
×
8 bits that
operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
•
High speed access time:10/12/15 nS (max.)
Low power consumption:
−
Active: 300 mW (typ.)
•
•
•
All inputs and outputs directly TTL/LVTTL
compatible
Three-state outputs
Available packages: 32-pin 300 mil SOJ,
skinny DIP and TSOP
•
•
Single +3.3V power supply
Fully static operation
PIN CONFIGURATIIONS
BLOCK DIAGRAM
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O 1
I/O 2
I/O 3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
V
SS
A0
.
.
A16
DECODER
CORE
C O RE
ARRAY
CS2
CS1
OE
WE
CONTROL
DATA I/O
I/O1
.
.
I/O8
PIN DESCRIPTION
SYMBOL
A0−A16
I/O1−I/O8
CS1, CS2
WE
OE
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A11
A9
A8
A13
WE
CS2
A15
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
DQ3
DQ2
DQ1
A0
A1
A2
A3
-1-
Publication Release Date: September 1999
Revision A2
W24L010A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
RATING
-0.5 to +4.6
-0.5 to V
DD
+0.5
1.0
-65 to +150
0 to +70
UNIT
V
V
W
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
TRUTH TABLE
CS1
H
X
L
L
L
CS2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
MODE
Not Selected
Not Selected
Output Disable
Read
Write
I/O1−I/O8
High Z
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB1
I
SB
, I
SB1
I
DD
I
DD
I
DD
OPERATING CHARACTERISTICS
(V
DD
= 3.3V
±5%,
V
SS
= 0V, T
A
= 0 to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
SYM.
V
IL
V
IH
I
LI
I
LO
V
OL
V
OH
I
DD
TEST CONDITIONS
-
-
V
IN
= V
SS
to V
DD
V
I/O
= V
SS
to V
DD
CS1 = V
IH
or CS2 = V
IL
or OE = V
IH
or WE = V
IL
I
OL
= +8.0 mA
I
OH
= -4.0 mA
10
CS1 = V
IL
,
CS2 = V
IH
I/O = 0 mA
Cycle = MIN
Duty = 100%
CS1
≥
V
DD
-0.2V or
CS2
≤
0.2V
12
15
MIN.
-0.5
+2.0
-10
-10
-
2.4
-
-
-
-
-
TYP.
-
-
-
-
-
-
-
-
-
-
-
MAX.
+0.8
V
DD
+0.5
+10
+10
0.4
-
130
120
100
15
5
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
Standby Power
Supply Current
I
SB
I
SB1
CS1 = V
IH
, or CS2 = V
IL
Note: Typical characteristics are at V
DD
= 3.3V, T
A
= 25° C.
-2-
W24L010A
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
8
10
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0V to 3V
3 nS
1.5V
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
CONDITIONS
AC TEST LOADS AND WAVEFORM
R1 320 ohm
R1 320 ohm
3.3V
OUTPUT
30 pF
Including
Jig and
Scope
R2
350 ohm
3.3V
OUTPUT
5 pF
Including
Jig and
Scope
R2
350 ohm
(For T
CLZ1,
T
CLZ2,
T
OLZ,
T
CHZ1,
T
CHZ2,
T
OHZ,
T
WHZ,
T
OW
)
3.0V
90%
10%
3 nS
10%
90%
0V
3 nS
-3-
Publication Release Date: September 1999
Revision A2
W24L010A
AC CHARACTERISTICS
(V
DD
= 3.3V
±5%,
V
SS
= 0V, T
A
= 0 to 70° C)
Read Cycle
PARAMETER
SYM.
W24L010A-
10
MIN.
Read Cycle Time
Address Access Time
Chip Select Access Time
CS1
CS2
Output Enable to Output Valid
Chip Selection to Output in
Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in
High Z
CS1
CS2
CS1
CS2
T
RC
T
AA
T
ACS1
T
ACS2
T
AOE
T
CLZ1*
T
CLZ2*
T
OLZ*
T
CHZ1*
T
CHZ2*
T
OHZ*
T
OH
10
-
-
-
-
3
3
0
-
-
-
3
MAX.
-
10
10
10
5
-
-
-
5
5
5
-
W24L010A-
12
MIN.
12
-
-
-
-
3
3
0
-
-
-
3
MAX.
-
12
12
12
6
-
-
-
6
6
6
-
W24L010A-
15
MIN.
15
-
-
-
-
3
3
0
-
-
-
3
MAX.
-
15
15
15
7
-
-
-
7
7
7
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
Output Disable to Output in High Z
Output Hold from Address Change
*
These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W24L010A-
10
MIN.
Write Cycle Time
Chip Selection to End of
CS1
T
WC
T
CW1
T
CW2
T
AW
T
AS
T
WP
T
WR1
T
WR2
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
10
9
9
9
0
9
0
0
5
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
-
-
5
5
-
W24L010A-
12
MIN.
12
10
10
10
0
10
0
0
7
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
-
-
6
6
-
W24L010A-
15
MIN.
15
13
13
13
0
10
0
0
9
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
8
8
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
Write
CS2
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery
CS1
,
WE
Time
CS2
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
*
These parameters are sampled but not 100% tested.
-4-
W24L010A
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
T
OH
D
OUT
T
AA
T
OH
Read Cycle 2
(Chip Select Controlled)
CS1
T
ACS1
CS2
T
ACS2
T
CHZ2
T
CHZ1
T
CLZ1
D
OUT
T
CLZ2
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
OE
T
AOE
CS1
T
OLZ
T
ACS1
T
CLZ1
CS2
T
ACS2
T
CLZ2
D
OUT
T
CHZ2
T
OHZ
T
CHZ1
T
OH
-5-
Publication Release Date: September 1999
Revision A2
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