CS4201
CrystalClear
Audio Codec ’97 with Headphone Amplifier
Features
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Integrated
High-Performance Headphone
Amplifier
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On-chip PLL for use with External Clock
Sources
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Sample Rate Converters
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S/PDIF Digital Audio Output
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AC ’97 2.1 Compliant
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20-bit Stereo Digital-to-Analog Converters
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18-bit Stereo Analog-to-Digital Converters
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Three Analog Line-level Stereo Inputs for
LINE IN, VIDEO, and AUX
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Two Analog Line-level Mono Inputs for
Modem and PC Beep
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Dual Microphone Inputs
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High Quality Pseudo-Differential CD Input
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Integrated High-Performance Microphone
Pre-Amplifier
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Separate Stereo Line-level Output
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Extensive Power Management Support
or Exceeds the Microsoft
PC 99 and
PC 2001 Audio Performance Requirements
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CrystalClear
3D Stereo Enhancement
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I
2
S Serial Digital Outputs Enable Cost
Effective Six Channel Applications
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Meets
Description
The CS4201 is an AC ’97 2.1 compliant stereo audio co-
dec designed for PC multimedia systems. It uses
industry leading CrystalClear
delta-sigma and mixed
signal technology. This advanced technology and these
features are designed to help enable the design of PC 99
and PC 2001 compliant high-quality audio systems for
desktop, portable, and entertainment PCs.
Coupling the CS4201 with a PCI audio accelerator or
core logic supporting the AC ’97 interface, implements a
cost effective, superior quality audio solution. The
CS4201 surpasses PC 99, PC 2001, and AC ’97 2.1 au-
dio quality standards.
ORDERING INFO
CS4201-JQ 48-pin TQFP
9x9x1.4 mm
AC-LINK AND AC ’97
REGISTERS
ANALOG INPUT MUX
AND OUTPUT MIXER
TEST
PWR
MGT
SRC
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
ID0#
ID1#
PCM_DATA
18 bit
ADC
INPUT
MUX
LINE
CD
AUX
VIDEO
MIC1
MIC2
PHONE
PC_BEEP
AC-
LINK
INPUT
MIXER
GAIN / MUTE CONTROLS
MIXER / MUX SELECTS
AC’97
REGISTERS
Σ
3D Stereo
Enhancement
OUTPUT
MIXER
GPIO0/LRCLK
GPIO1/SDOUT
EAPD/SCLK
SPDO/SDO2
GPIO, S/PDIF
SERIAL DATA PORT
SRC
PCM_DATA
20 bit
DAC
Σ
LINE_OUT
HP_OUT
MONO_OUT
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
Cirrus Logic, Inc. 2001
(All Rights Reserved)
APR ‘01
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CS4201
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................7
Analog Characteristics ........................................................................................................7
Absolute Maximum Ratings ................................................................................................8
Recommended Operating Conditions.................................................................................8
AC ’97 Serial Port Timing..................................................................................................10
2. GENERAL DESCRIPTION ...............................................................................................13
2.1 AC-Link ......................................................................................................................13
2.2 Control Registers .......................................................................................................14
2.3 Sample Rate Converters ...........................................................................................14
2.4 Mixers ........................................................................................................................14
2.5 Input Mux ...................................................................................................................14
2.6 Volume Control ..........................................................................................................14
3. AC-LINK FRAME DEFINITION ........................................................................................16
3.1 AC-Link Serial Data Output Frame ............................................................................17
3.1.1 Serial Data Output Slot Tags (Slot 0) ...........................................................17
3.1.2 Command Address Port (Slot 1) ..................................................................17
3.1.3 Command Data Port (Slot 2) ........................................................................18
3.1.4 PCM Playback Data (Slots 3-11) .................................................................18
3.1.5 GPIO Pin Control (Slot12) ............................................................................18
3.2 AC-Link Serial Data Input Frame ..............................................................................19
3.2.1 Serial Data Input Slot Tag Bits (Slot 0) ......................................................19
3.2.2 Status Address Port (Slot 1) .........................................................................19
3.2.3 Status Data Port (Slot 2) ..............................................................................20
3.2.4 PCM Capture Data (Slot 3-8) .......................................................................20
3.2.5 GPIO Pin Status (Slot 12) ...........................................................................20
3.3 AC-Link Protocol Violation - Loss of SYNC ...............................................................21
4. REGISTER INTERFACE
.............................................................................................22
4.1 Reset Register (Index 00h) ......................................................................................23
4.2 Analog Mixer Output Volume Registers (Index 02h - 04h) ......................................23
4.3 Mono Volume Register (Index 06h) ..........................................................................24
4.4 PC_BEEP Volume Register (Index 0Ah) ..................................................................24
4.5 Phone Volume Register (Index 0Ch) ........................................................................24
4.6 Microphone Volume Register (Index 0Eh) ................................................................25
4.7 Analog Mixer Input Gain Registers (Index 10h - 18h) ...............................................26
4.8 Input Mux Select Register (Index 1Ah) .....................................................................27
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries.
Intel is a registered trademark of Intel Corporation.
CrystalClear is a registered trademark of Cirrus Logic.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any
kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third
parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publi-
cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise)
without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the
printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photo-
graphic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or
sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in
this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
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CS4201
4.9 Record Gain Register (Index 1Ch) ........................................................................... 27
4.10 General Purpose Register (Index 20h) ................................................................. 28
4.11 3D Control Register (Index 22h) ............................................................................. 28
4.12 Powerdown Control/Status Register (Index 26h) ................................................... 29
4.13 Extended Audio ID Register (Index 28h) ................................................................ 30
4.14 Extended Audio Status/Control Register (Index 2Ah) ............................................ 30
4.15 Audio Sample Rate Control Registers (Index 2Ch - 32h) ....................................... 31
4.16 Extended Modem ID Register (Index 3Ch) ............................................................ 32
4.17 Extended Modem Status/Control Register (Index 3Eh) ......................................... 32
4.18 GPIO Pin Configuration Register (Index 4Ch) ........................................................32
4.19 GPIO Pin Polarity/Type Configuration Register (Index 4Eh) .................................. 33
4.20 GPIO Pin Sticky Register (Index 50h) .................................................................... 33
4.21 GPIO Pin Wakeup Mask Register (Index 52h) ...................................................... 34
4.22 GPIO Pin Status Register (Index 54h) ................................................................... 34
4.23 AC Mode Control Register (Index 5Eh) .................................................................. 35
4.24 Misc. Crystal Control Register (Index 60h) ............................................................. 36
4.25 S/PDIF Control Register (Index 68h) ...................................................................... 37
4.26 Serial Port Control Register (Index 6Ah) ................................................................ 38
4.27 Vendor ID1 Register (Index 7Ch) ........................................................................... 39
4.28 Vendor ID2 Register (Index 7Eh) ........................................................................... 39
5. SERIAL DATA PORTS ..................................................................................................... 40
5.1 Overview ................................................................................................................... 40
5.2 Multi-Channel Expansion .......................................................................................... 40
5.3 Serial Data Formats .................................................................................................. 41
6. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ............................................................. 43
7. EXCLUSIVE FUNCTIONS ................................................................................................ 44
8. POWER MANAGEMENT ................................................................................................. 45
8.1 AC ’97 Reset Modes ................................................................................................. 45
8.1.1 Cold Reset ................................................................................................... 45
8.1.2 Warm Reset ................................................................................................. 45
8.1.3 New Warm Reset .........................................................................................45
8.1.4 Register Reset ............................................................................................. 45
8.2 Powerdown Controls ................................................................................................. 46
9. CLOCKING ....................................................................................................................... 48
9.1 PLL Operation (External Clock) ................................................................................ 48
9.2 24.576 MHz Crystal Operation ..................................................................................48
9.3 Secondary Codec Operation ..................................................................................... 48
10. ANALOG HARDWARE DESCRIPTION ......................................................................... 50
10.1Analog Inputs ............................................................................................................50
10.1.1 Line Inputs ................................................................................................. 50
10.1.2 CD Input ..................................................................................................... 50
10.1.3 Microphone Inputs ..................................................................................... 51
10.1.4 PC Beep Input ............................................................................................ 51
10.1.5 Phone Input ................................................................................................ 51
10.2Analog Outputs ......................................................................................................... 52
10.2.1 Stereo Outputs ........................................................................................... 52
10.2.2 Mono Output .............................................................................................. 52
10.3Miscellaneous Analog Signals ..................................................................................52
10.4Power Supplies ......................................................................................................... 53
10.5Reference Design ..................................................................................................... 53
11. GROUNDING AND LAYOUT ........................................................................................ 54
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CS4201
12. PIN DESCRIPTIONS ..................................................................................................56
Audio I/O Pins .................................................................................................................57
Analog Reference, Filter, and Configuration Pins ...........................................................58
AC-Link Pins ...................................................................................................................59
Clock and Configuration Pins ..........................................................................................60
Misc. Digital Interface Pins ..............................................................................................60
Power Supply Pins ..........................................................................................................61
13. PARAMETER AND TERM DEFINITIONS ......................................................................62
14. REFERENCE DESIGN .................................................................................................64
15. REFERENCES ................................................................................................................65
16. PACKAGE DIMENSIONS ...............................................................................................66
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CS4201
LIST OF FIGURES
Figure 1. Power Up Timing ...............................................................................................11
Figure 2. Codec Ready from Start-up or Fault Condition ................................................. 11
Figure 3. Clocks................................................................................................................ 11
Figure 4. Data Setup and Hold .........................................................................................12
Figure 5. PR4 Powerdown and Warm Reset.................................................................... 12
Figure 6. Test Mode ......................................................................................................... 12
Figure 7. AC-link Connections .......................................................................................... 13
Figure 8. CS4201 Mixer Diagram ..................................................................................... 15
Figure 9. AC-link Input and Output Framing .....................................................................16
Figure 10. Serial Data Port: Six Channel Circuit .............................................................. 40
Figure 11. Serial Data Format 0 (I2S) .............................................................................. 42
Figure 12. Serial Data Format 1 (Left Justified)................................................................ 42
Figure 13. Serial Data Format 2 (Right Justified, 20-bit data) .......................................... 42
Figure 14. Serial Data Format 3 (Right Justified, 16-bit data) .......................................... 42
Figure 15. S/PDIF Output ................................................................................................. 43
Figure 16. PLL External Loop Filter ..................................................................................48
Figure 17. External Crystal ...............................................................................................48
Figure 18. Line Input (Replicate for Video and AUX) ....................................................... 50
Figure 19. Differential 2 VRMS CD Input.......................................................................... 50
Figure 20. Differential 1 VRMS CD Input.......................................................................... 50
Figure 21. Microphone Input............................................................................................. 51
Figure 22. PC_BEEP Input ...............................................................................................51
Figure 23. Modem Connection .........................................................................................51
Figure 24. Line Out and Headphone Out Setup ...............................................................52
Figure 25. Line Out/Headphone Out Setup ...................................................................... 52
Figure 26. +5V Analog Voltage Regulator ........................................................................ 53
Figure 27. Conceptual Layout for the CS4201 when in XTAL or OSC Clocking Modes .. 55
Figure 28. Pin Locations for the CS4201.......................................................................... 56
Figure 29. CS4201 Reference Design.............................................................................. 64
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