INTEGRATED CIRCUITS
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
Positive specification
IC15 Data Handbook
1990 Sep 14
Philips
Semiconductors
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
FEATURES
•
Metastable immune characteristics
•
Output skew less than 1.5ns
•
See 74F5074 for synchronizing dual D-type flip-flop
•
See 74F50109 for synchronizing dual J–K positive edge-triggered
flip-flop
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output. Data entering the 74F50728 requires two
clock cycles to arrive at the outputs.
The 74F50728 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50728
are:
τ ≅ 135ps
and T
0
≅
9.8 X 10
6
sec where
τ
represents a
function of the rate at which a latch in a metastable state resolves
that condition and T
o
represents a function of the measurement of
the propensity of a latch to enter a metastable state.
TYPICAL SUPPLY
CURRENT (TOTAL)
23mA
•
See 74F50729
for synchronizing dual dual D-type flip-flop with
edge-triggered set and reset
•
Industrial temperature range available (–40
°
C to +85
°
C)
DESCRIPTION
The 74F50728 is a cascaded dual positive edge–triggered D–type
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. They set and reset
both flip–flops of a cascaded pair simultaneously. Data must be
stable just one setup time prior to the low–to–high transition of the
clock for guaranteed propagation delays.
TYPE
74F50728
TYPICAL f
max
145 MHz
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
DESCRIPTION
T
amb
= 0
°
C to +70
°
C
14–pin plastic DIP
14–pin plastic SO
N74F50728N
N74F50728D
V
CC
= 5V
±
10%,
INDUSTRIAL RANGE
T
amb
= –40
°
C to +85
°
C
I74F50728N
I74F50728D
SOT27-1
SOT108-1
V
CC
= 5V
±
10%,
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0, D1
CP0, CP1
SD0, SD1
RD0, RD1
Data inputs
Clock inputs (active rising edge)
Set inputs (active low)
Reset inputs (active low)
DESCRIPTION
74F (U.L.) HIGH/
LOW
1.0/0.417
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE HIGH/
LOW
20µA/250µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
Q0, Q1, Q0, Q1
Data outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
September 14, 1990
2
853-1389 00421
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
PIN CONFIGURATION
LOGIC DIAGRAM
4, 10
SDn
RD0 1
D0 2
CP0 3
SD0 4
Q0 5
Q0 6
GND 7
14 V
CC
13 RD1
12 D1
11 CP1
10 SD1
9 Q1
8 Q1
V
cc
= Pin 14
GND = Pin 7
CPn
RDn
3, 11
1, 13
2, 12
Dn
D
Q
D
Q
5, 9
Qn
6, 8
Qn
CP Q
CP Q
SF00608
SF00605
NOTE:
Data entering the flip–flop requires two clock cycles to
arrive at the output.
LOGIC SYMBOL
SYNCHRONIZING SOLUTIONS
2
12
D0 D1
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
5
V
CC
= Pin 14
GND = Pin 7
6
9
8
SF00606
IEC/IEEE SYMBOL
4
3
2
1
1D
6
R
&
S
C1
3
Synchronizing incoming signals to a system clock has proven to be
costly, either in terms of time delays or hardware. The reason for this
is that in order to synchronize the signals a flip–flop must be used to
”capture” the incoming signal. While this is perhaps the only way to
synchronize a signal, to this point, there have been problems with
this method. Whenever the flop’s setup or hold times are violated
the flop can enter a metastable state causing the outputs in turn to
glitch, oscillate, enter an intermediate state or change state in some
abnormal fashion. Any of these conditions could be responsible for
causing a system crash. To minimize this risk, flip–flops are often
cascaded so that the input signal is captured on the first clock pulse
and released on the second clock pulse (see Fig.1). This gives the
first flop about one clock period minus the flop delay and minus the
second flop’s clock–to–Q setup time to resolve any metastable
condition. This method greatly reduces the probability of the outputs
of the synchronizing device displaying an abnormal state but the
trade-off is that one clock cycle is lost to synchronize the incoming
data and two separate flip–flops are required to produce the
cascaded flop circuit. In order to assist the designer of synchronizing
circuits Philips Semiconductors is offering the 74F50728.
DATA
CLOCK
D
Q
D
Q
Q OUTPUT
Q OUTPUT
CP Q
CP Q
10
11
12
13
S
C2
9
SF00609
Figure 1.
2D
8
R
SF00607
The 50728 consists of two pair of cascaded D–type flip–flops with
metastable immune features and is pin compatible with the 74F74.
Because the flops are cascaded on a single part the metastability
September 14, 1990
3
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
characteristics are greatly improved over using two separate flops
that are cascaded. The pin compatibility with the 74F74 allows for
plug–in retrofitting of previously designed systems.
Because the probability of failure of the 74F50728 is so remote, the
metastability characteristics of the part were empirically determined
based on the characteristics of its sister part, the 74F5074. The
table below shows the 74F5074 metastability characteristics.
Having determined the T
0
and
τ
of the flop, calculating the mean
time between failures (MTBF) for the 74F50728 is simple. It is,
however, somewhat different than calculating MTBF for a typical part
because data requires two clock pulses to transit from the input to
the output. Also, in this case a failure is considered of the output
beyond the normal propagation delay.
Suppose a designer wants to use the flop for synchronizing
asynchronous data that is arriving at 10MHz (as measured by a
frequency counter), and is using a clock frequency of 50MHz. He
simply plugs his number into the equation below:
MTBF = e
(t’/t)
/T
o
f
C
f
I
In this formula, f
C
is the frequency of the clock, f
I
is the average
input event frequency, and t’ is the period of the clock input (20
nanoseconds). In this situation the f
I
will be twice the data
frequency of 20 MHz because input events consist of both of low
and high data transitions. From Fig. 2 it is clear that the MTBF is
greater than 10
41
seconds. Using the above formula the actual
MTBF is 2.23 X 10
42
seconds or about 7 X 10
34
years.
TYPICAL VALUES FOR
τ
AND T
0
AT VARIOUS V
CC
S AND TEMPERATURES
T
amb
= 0
°
C
τ
V
CC
= 5.5V
V
CC
= 5.0V
V
CC
= 4.5V
125ps
115ps
115ps
T
0
1.0 X 10
9
sec
1.3 X 10
10
sec
3.4 X 10
13
sec
τ
138ps
135ps
132ps
T
amb
= 25
°
C
T
0
5.4 X 10
6
sec
9.8 X 10
6
sec
5.1 X 10
8
sec
τ
160ps
167ps
175ps
T
amb
= 70
°
C
T
0
1.7 X 10
5
sec
3.9 X 10
4
sec
7.3 X 10
4
sec
MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY
10
70
Clock = 40MHz
10
60
10
50
Mean time
between failures
(seconds)
10
40
Clock = 650MHz
10
30
Clock = 70MHz
Clock = 80MHz
10
20
1 billion years
10
10
Clock = 100MHz
Clock = 50MHz
10
00
1K
NOTE: V
CC
= 5V, T
amb
= 25°C,
τ
=135ps, To = 9.8 X 10
8
sec
Data frequency (Hz)
100K
10M
SF00610
Figure 2.
September 14, 1990
4
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
FUNCTION TABLE
INTERNAL
INPUTS
SDn
L
H
L
H
H
H
RDn
H
L
L
H
H
H
CPn
X
X
X
↑
↑
L
Dn
X
X
X
h
l
X
REGISTER
Q
H
L
X
h
l
NC
OUTPUTS
Qn
H
L
H
H
L
NC
Qn
L
H
H
L
H
NC
Asynchronous set
Asynchronous reset
Undetermined*
Load ”1”
Load ”0”
Hold
OPERATING MODE
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low–to–high
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low–to–high
clock transition
NC= No change from the previous setup
X = Don’t care
* = This setup is unstable and will change when either set of
reset return to the high–level
↑
= Low–to–high clock transition.
** = Data entering the flip–flop requires two clock cycles to
arrive at the output (see logic diagram)
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Commercial range
Industrial range
T
stg
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°
C
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
High–level output current
Low–level output current
Operating free air temperature range
Commercial range
Industrial range
0
–40
4.5
2.4
0.8
–18
–3
20
+70
+85
LIMITS
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°
C
°
C
September 14, 1990
5
Test/Measurement
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