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SST89E554RC-40-C-NJE

Description
Microcontroller (mcu) 32kb+8kb 40ns
Categorysemiconductor    The embedded processor and controller   
File Size893KB,90 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Parametric View All

SST89E554RC-40-C-NJE Overview

Microcontroller (mcu) 32kb+8kb 40ns

SST89E554RC-40-C-NJE Parametric

Parameter NameAttribute value
MakerMicrochip
RoHSyes
Data bus width8 bi
Program memory typeFlash
Program memory size32 KB
Data RAM size1 KB
Interface TypeSPI/UART
maximum clock frequency40 MHz
Number of programmable input/output terminals32
Number of timers16 bi
Working power voltage4.5 V to 5.5 V
Maximum operating temperature+ 70 C
Installation styleSMD/SMT
Package/boxPLCC-44
EncapsulationTube
Minimum operating temperature0 C
FlashFlex MCU
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
EOL Data Sheet
FEATURES:
• 8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
• SST89E564RD/SST89E554RC Operation
– 0 to 40 MHz at 5V
• SST89V564RD/SST89V554RC Operation
– 0 to 33 MHz at 3V
• Total 1 KByte Internal RAM (256 Byte + 768 Byte)
• Dual Block SuperFlash EEPROM
– SST89E564RD/SST89V564RD:
64 KByte primary block + 8 KByte secondary
block (128-Byte sector size for both blocks)
– SST89E554RC/SST89V554RC:
32 KByte primary block + 8 KByte secondary
block (128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during
In-Application Programming (IAP)
– Memory Overlay for Interrupt Support
during IAP
• Support External Address Range up to 64
KByte of Program and Data Memory
• Three High-Current Drive Port 1 pins
• Three 16-bit Timers/Counters
• Full-Duplex, Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Eight Interrupt Sources at 4 Priority Levels
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins)
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Brown-out Detection
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
• Packages Available
– 40-contact WQFN
– 44-lead PLCC
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
– Non-Pb (lead-free) packages available
In addition to the 72/40 KByte of EEPROM on-chip pro-
gram memory and 1024 x8 bits of on-chip RAM, the
devices can address up to 64 KByte of external program
memory and up to 64 KByte of external RAM.
The flash memory blocks can be programmed via a stan-
dard 87C5x OTP EPROM programmer fitted with a special
adapter and the firmware for SST’s devices. During power-
on reset, the devices can be configured as either a slave to
an external host for source code storage or a master to an
external host for an in-application programming (IAP) oper-
ation. The devices are designed to be programmed in-sys-
tem and in-application on the printed circuit board for
maximum flexibility. The devices are pre-programmed with
an example of the bootstrap loader in memory, demonstrat-
ing the initial user program code loading or subsequent
user code updating via an IAP operation. A sample boot-
strap loader is available for the user’s reference and conve-
nience only; SST does not guarantee its functionality or
usefulness. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
PRODUCT DESCRIPTION
The SST89E564RD, SST89V564RD, SST89E554RC, and
SST89V554RC are members of the FlashFlex family of 8-bit
microcontroller products designed and manufactured with
SST’s patented and proprietary SuperFlash CMOS semi-
conductor process technology. The split-gate cell design
and thick-oxide tunneling injector offer significant cost and
reliability benefits for our customers. The devices use the
8051 instruction set and are pin-for-pin compatible with stan-
dard 8051 microcontroller devices.
The devices come with 72/40 KByte of on-chip flash
EEPROM program memory which is partitioned into 2
independent program memory blocks. The primary Block 0
occupies 64/32 KByte of internal program memory space
and the secondary Block 1 occupies 8 KByte of internal
program memory space.
The 8-KByte secondary flash block can be mapped to the
lowest location of the 64-/32-KByte address space; it can
also be hidden from the program counter and used as an
independent EEPROM-like data memory.
©2007 Silicon Storage Technology, Inc.
S71207-08-EOL
1/07
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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