ISP1160
Embedded Universal Serial Bus Host Controller
Rev. 04 — 04 July 2003
Product data
1. General description
The ISP1160 is an embedded Universal Serial Bus (USB) Host Controller (HC) that
complies with
Universal Serial Bus Specification Rev. 2.0,
supporting data transfer at
full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1160 provides two
downstream ports. Each downstream port has an overcurrent (OC) detection input
pin and power supply switching control output pin. The downstream ports for the HC
can be connected with any USB compliant USB devices and USB hubs that have
USB upstream ports.
The ISP1160 is well suited for embedded systems and portable devices that require a
USB host. The ISP1160 brings high flexibility to the systems that have it built-in. For
example, a system that has the ISP1160 built-in allows it to be connected to a device
that has a USB upstream port, such as a USB printer, USB camera, USB keyboard,
USB mouse, among others.
2. Features
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Complies with
Universal Serial Bus Specification Rev. 2.0
Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
Adapted from
Open Host Controller Interface Specification for USB Release 1.0a
Selectable one or two downstream ports for HC
High-speed parallel interface to most of the generic microprocessors and
Reduced Instruction Set Computer (RISC) processors such as:
x
Hitachi
®
SuperH™ SH-3 and SH-4
x
MIPS-based™ RISC
x
ARM7™, ARM9™, and StrongARM
®
Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC
Supports single-cycle and burst mode DMA operations
Built-in FIFO buffer RAM for the HC (4 kbytes)
Endpoints with double buffering to increase throughput and ease real-time data
transfer for isochronous (ISO) transactions
6 MHz crystal oscillator with integrated PLL for low EMI
Built-in software selectable internal 15 kΩ pull-down resistors for HC downstream
ports
Dedicated pins for suspend sensing output and wake-up control input for flexible
applications
Operation at either
+5
V or
+3.3
V power supply voltage
Operating temperature range from
−40 °C
to
+85 °C
Available in two LQFP64 packages (SOT314-2 and SOT414-1).
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
3. Applications
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Personal Digital Assistant (PDA)
Digital camera
Third-generation (3-G) phone
Set-Top Box (STB)
Information Appliance (IA)
Photo printer
MP3 jukebox
Game console.
4. Ordering information
Table 1:
Ordering information
Package
Name
ISP1160BD
ISP1160BD/01
[1]
ISP1160BM
ISP1160BM/01
[2]
[1]
[2]
Type number
Description
plastic low profile quad flat package; 64 leads;
body 10
×
10
×
1.4 mm
plastic low profile quad flat package; 64 leads;
body 7
×
7
×
1.4 mm
Version
SOT314-2
SOT414-1
LQFP64
LQFP64
Improvement in performance as compared to ISP1160BD.
Improvement in performance as compared to ISP1160BM.
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
2 of 88
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Product data
Rev. 04 — 04 July 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11371
5. Block diagram
Philips Semiconductors
H_WAKEUP
H_SUSPEND
NDP_SEL
40
42
33
ATL RAM
ITL0
(PING RAM)
2 to 7,
9 to 14,
16, 17,
63, 64
22
21
23
59
27
34
25
29
ITL1
(PONG RAM)
POWER
SWITCHING
OVERCURRENT
DETECTION
46
47
54
55
H_PSW1_N
H_PSW2_N
H_OC1_N
H_OC2_N
16
D0 to D15
RD_N
CS_N
WR_N
A0
DACK_N
EOT
DREQ
INT
ISP1160
50
MICROPROCESSOR
BUS INTERFACE
USB
TRANSCEIVER
HOST CONTROLLER
USB
TRANSCEIVER
51
52
53
H_DM1
H_DP1
H_DM2
H_DP2
USB bus
downstream
ports
RESET_N
32
4×
15 kΩ
POWER-ON
RESET
internal
reset
CLOCK
RECOVERY
VCC
56
VOLTAGE
REGULATOR
1, 8, 15, 18,
35, 45, 62
7
3.3 V
internal
supply
PLL
CLOCK
RECOVERY
GND
Embedded USB Host Controller
57
58
24
19
XTAL2
44
43
XTAL1
20, 26, 30, 31, 36,
38, 41, 48, 49, 61
DGND
AGND
VREG(3V3)
VHOLD2
10
n.c.
004aaa059
VHOLD1
6 MHz
ISP1160
3 of 88
Fig 1. Block diagram.
Philips Semiconductors
ISP1160
Embedded USB Host Controller
6. Pinning information
6.1 Pinning
58 VREG(3V3)
55 H_OC2_N
54 H_OC1_N
60 LOW_PW
52 H_DM2
50 H_DM1
53 H_DP2
51 H_DP1
62 DGND
57 AGND
56 VCC
61 n.c.
64 D1
63 D0
DGND 1
D2 2
D3 3
D4 4
D5 5
D6 6
D7 7
DGND 8
D8 9
D9 10
D10 11
D11 12
D12 13
D13 14
DGND 15
D14 16
CS_N 21
n.c. 20
RD_N 22
WR_N 23
VHOLD2 24
DREQ 25
n.c. 26
DACK_N 27
TEST_HIGH 28
INT 29
n.c. 30
n.c. 31
RESET_N 32
D15 17
DGND 18
VHOLD1 19
59 A0
49 n.c.
48 n.c.
47 H_PSW2_N
46 H_PSW1_N
45 DGND
44 XTAL2
43 XTAL1
ISP1160BD
ISP1160BM
ISP1160BD/01
ISP1160BM/01
42 H_SUSPEND
41 n.c.
40 H_WAKEUP
39 TEST_LOW
38 n.c.
37 TEST_LOW
36 n.c.
35 DGND
34 EOT
33 NDP_SEL
004aaa060
Fig 2. Pin configuration LQFP64.
6.2 Pin description
Table 2:
Symbol
[1]
DGND
D2
D3
D4
Pin description for LQFP64
Pin
1
2
3
4
Type
-
I/O
I/O
I/O
Description
digital ground
bit 2 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 3 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 4 of bidirectional data; slew-rate controlled; TTL input;
three-state output
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
4 of 88
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Pin description for LQFP64
…continued
Pin
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Type
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
-
-
Description
bit 5 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 6 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 7 of bidirectional data; slew-rate controlled; TTL input;
three-state output
digital ground
bit 8 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 9 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 10 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 11 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 12 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 13 of bidirectional data; slew-rate controlled; TTL input;
three-state output
digital ground
bit 14 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 15 of bidirectional data; slew-rate controlled; TTL input;
three-state output
digital ground
voltage holding pin 1; internally connected to the V
REG(3V3)
and V
HOLD2
pins. When V
CC
is connected to 5 V, this pin
will output 3.3 V, hence do not connect it to 5 V. When V
CC
is connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In
all
cases, decouple this pin to
DGND.
no connection; leave this pin open
chip select input
read strobe input
write strobe input
voltage holding pin 2; internally connected to the V
REG(3V3)
and V
HOLD1
pins. When V
CC
is connected to 5 V, this pin
will output 3.3 V, hence do not connect it to 5 V. When V
CC
is connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In
all
cases, decouple this pin to
DGND.
HC DMA request output (programmable polarity); signals
to the DMA controller that the ISP1160 wants to start a
DMA transfer; see
Section 10.4.1
no connection; leave this pin open
Table 2:
Symbol
[1]
D5
D6
D7
DGND
D8
D9
D10
D11
D12
D13
DGND
D14
D15
DGND
V
HOLD1
n.c.
CS_N
RD_N
WR_N
V
HOLD2
20
21
22
23
24
-
I
I
I
-
DREQ
25
O
n.c.
26
-
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
5 of 88
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