a
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
8-Bit Resolution
Linearity: 1/4 LSB DNL
Linearity:
1/4 LSB INL
Differential Current Outputs
SINAD @ 5 MHz Output: 50 dB
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and 28-Lead TSSOP
Edge-Triggered Latches
Fast Settling: 35 ns Full-Scale Settling to 0.1%
APPLICATIONS
Communications
Signal Reconstruction
Instrumentation
PRODUCT DESCRIPTION
8-Bit, 100 MSPS+
TxDAC
®
D/A Converter
AD9708*
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1 F
REFLO
+1.20V REF
0.1 F
REF IO
FS ADJ
R
SET
+5V
DVDD
DCOM
CLOCK
SLEEP
COMP1
AVDD
ACOM
50pF
CURRENT
SOURCE
ARRAY
SEGMENTED
SWITCHES
LATCHES
AD9708
COMP2
0.1 F
IOUTA
IOUTB
CLOCK
DIGITAL DATA INPUTS (DB7–DB0)
Differential current outputs are provided to support single-
ended or differential applications. The current outputs may be
directly tied to an output resistor to provide two complemen-
tary, single-ended voltage outputs. The output voltage compliance
range is 1.25 V.
The AD9708 contains a 1.2 V on-chip reference and reference
control amplifier, which allows the full-scale output current to
be simply set by a single resistor. The AD9708 can be driven by
a variety of external reference voltages. The AD9708’s full-scale
current can be adjusted over a 2 mA to 20 mA range without
any degradation in dynamic performance. Thus, the AD9708
may operate at reduced power levels or be adjusted over a 20 dB
range to provide additional gain ranging capabilities.
The AD9708 is available in 28-lead SOIC and 28-lead TSSOP
packages. It is specified for operation over the industrial tem-
perature range.
PRODUCT HIGHLIGHTS
The AD9708 is the 8-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, was specifically opti-
mized for the transmit signal path of communication systems. All
of the devices share the same interface options, small outline
package and pinout, thus providing an upward or downward
component selection path based on performance, resolution and
cost. The AD9708 offers exceptional ac and dc performance
while supporting update rates up to 125 MSPS.
The AD9708’s flexible single-supply operating range of +2.7 V
to +5.5 V and low power dissipation are well suited for portable
and low power applications. Its power dissipation can be
further reduced to 45 mW, without a significant degradation in
performance, by lowering the full-scale current output. In addi-
tion, a power-down mode reduces the standby power dissipa-
tion to approximately 20 mW.
The AD9708 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
The AD9708 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
*Patent
pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
1. The AD9708 is a member of the TxDAC product family, which
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9708 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance well beyond 8- and 10-bit video DACs.
3. On-chip, edge-triggered input CMOS latches readily interface
to +3 V and +5 V CMOS logic families. The AD9708 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of +2.7 V to +5.5 V
and a wide full-scale current adjustment span of 2 mA to
20 mA allows the AD9708 to operate at reduced power levels
(i.e., 45 mW) without any degradation in dynamic performance.
5. A temperature compensated, 1.20 V bandgap reference is
included on-chip providing a complete DAC solution. An
external reference may be used.
6. The current output(s) of the AD9708 can easily be config-
ured for various single-ended or differential applications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9708–SPECIFICATIONS
DC SPECIFICATIONS
(T
Parameter
RESOLUTION
MONOTONICITY
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o C
COMP1
)
4
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
5
DVDD
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
6
Supply Current Sleep Mode (I
AVDD
)
Power Dissipation
6
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(3 V, I
OUTFS
= 2 mA)
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
OPERATING RANGE
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
Min
8
Typ
Max
Units
Bits
GUARANTEED OVER SPECIFIED TEMPERATURE RANGE
–1/2
–1/2
–0.025
–10
–10
2.0
–1.0
±
1/4
±
1/4
+1/2
+1/2
+0.025
+10
+10
20.0
1.25
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
MΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
±
2
±
1
100
5
1.08
1.20
100
1.32
0.1
1
1.4
0
±
50
±
100
±
50
1.25
2.7
2.7
5.0
5.0
25
3
140
190
45
5.5
5.5
30
6
8.5
175
–0.4
–0.025
–40
+0.4
+0.025
+85
V
V
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32
×
the I
REF
current.
3
Use an external buffer amplifier to drive any external load.
4
Reference bandwidth is a function of external cap at COMP1 pin.
5
For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6
Measured at f
CLOCK
= 50 MSPS and f
OUT
= 1.0 MHz.
7
Measured as unbuffered voltage output into 50
Ω
R
LOAD
at IOUTA and IOUTB, f
CLOCK
= 100 MSPS and f
OUT
= 40 MHz.
Specifications subject to change without notice.
–2–
REV. B
AD9708
DYNAMIC SPECIFICATIONS
P
arameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
)
Output Settling Time (t
ST
) (to 0.1%)
1
Output Propagation Delay (t
PD
)
Glitch Impulse
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
1
Output Noise (I
OUTFS
= 20 mA)
Output Noise (I
OUTFS
= 2 mA)
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion Ratio
f
CLOCK
= 10 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 12.51 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 5.01 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 25.01 MHz
Total Harmonic Distortion
f
CLOCK
= 10 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 12.51 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 5.01 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 25.01 MHz
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 10 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 12.51 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 5.01 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 25.01 MHz
NOTES
1
Measured single ended into 50
Ω
load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Single-Ended Output, IOUTA, 50
Terminated, unless otherwise noted)
Min
100
Typ
125
35
1
5
2.5
2.5
50
30
Max
Doubly
Units
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
50
50
48
50
45
–67
–67
–59
–64
–48
62
68
68
63
67
50
–62
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
DIGITAL SPECIFICATIONS
(T
P
arameter
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
Specifications subject to change without notice.
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
Min
3.5
2.1
–10
–10
5
2.0
1.5
Typ
5
3
0
0
Max
Units
V
V
V
V
µA
µA
pF
ns
ns
1.3
0.9
+10
+10
3.5
ns
DB0–DB7
t
S
CLOCK
t
H
t
LPW
t
PD
t
ST
0.1%
0.1%
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
REV. B
–3–
AD9708
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
COMP1, COMP2
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
With
Respect to
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+0.3
+150
+150
+300
Units
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
PIN FUNCTION DESCRIPTIONS
Pin No. Name
1
2–7
8
9–14, 25
15
DB7
DB6–DB1
DB0
NC
SLEEP
Description
Most Significant Data Bit (MSB).
Data Bits 1–6.
Least Significant Data Bit (LSB).
No Internal Connection.
Power-Down Control Input. Active
High. Contains active pull-down circuit,
thus may be left unterminated if not
used.
Reference Ground when Internal 1.2 V
Reference Used. Connect to AVDD to
disable internal reference.
Reference Input/Output. Serves as
reference input when internal reference
disabled (i.e., Tie REFLO to AVDD).
Serves as 1.2 V reference output when
internal reference activated (i.e., Tie
REFLO to ACOM). Requires 0.1
µF
capacitor to ACOM when internal
reference activated.
Full-Scale Current Output Adjust.
Bandwidth/Noise Reduction Node.
Add 0.1
µF
to AVDD for optimum
performance.
Analog Common.
Complementary DAC Current Output.
Full-scale current when all data bits
are 0s.
DAC Current Output. Full-scale
current when all data bits are 1s.
Internal Bias Node for Switch Driver
Circuitry. Decouple to ACOM with
0.1
µF
capacitor.
Analog Supply Voltage (+2.7 V to
+5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to
+5.5 V).
Clock Input. Data latched on positive
edge of clock.
16
REFLO
17
REFIO
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
18
19
FS ADJ
COMP1
28-Lead 300 mil SOIC
θ
JA
= 71.4°C/W
θ
JC
= 23°C/W
28-Lead TSSOP
θ
JA
= 97.9°C/W
θ
JC
= 14.0°C/W
PIN CONFIGURATION
28 CLOCK
27 DVDD
26 DCOM
25 NC
20
21
ACOM
IOUTB
22
23
IOUTA
COMP2
(MSB) DB7 1
DB6 2
DB5 3
DB4 4
DB3 5
DB2 6
24
26
27
28
AVDD
DCOM
DVDD
CLOCK
AD9708
24 AVDD
TOP VIEW 23 COMP2
(Not to Scale) 22 IOUTA
DB1 7
21 IOUTB
20 ACOM
19 COMP1
18 FS ADJ
17 REFIO
16 REFLO
15 SLEEP
DB0 8
NC 9
NC 10
NC 11
NC 12
NC 13
NC 14
ORDERING GUIDE
Temperature
Range
Package
Descriptions
Package
Options*
Model
NC = NO CONNECT
AD9708AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9708ARU –40°C to +85°C 28-Lead TSSOP
RU-28
AD9708-EB Evaluation Board
*R = Small Outline IC; RU = Thin Small Outline IC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9708 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
AD9708
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
Total Harmonic Distortion
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T
MIN
or T
MAX
. For
+5V
0.1 F
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).
REFLO
+1.20V REF
0.1 F
REF IO
FS ADJ
R
SET
2k
+5V
DVDD
DCOM
CLOCK
DVDD
DCOM
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
COMP1
50pF
AVDD
ACOM
AD9708
CURRENT
SOURCE
ARRAY
COMP2
0.1 F
IOUTA
SEGMENTED
SWITCHES
LATCHES
IOUTB
50
20pF
50
SLEEP
50
CLOCK
OUTPUT
DIGITAL
DATA
TEKTRONIX
AWG-2021
20pF
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50 INPUT
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
Figure 2. Basic AC Characterization Test Setup
REV. B
–5–
京公网安备 11010802033920号
EEWORLD
