CS4205
CrystalClear
®
Audio Codec ’97 for Portable Computing
Features
!
Integrated
!
Three
Asynchronous I
2
S Input Port
(ZV Port)
!
Integrated High-Performance Microphone
Pre-Amplifier
!
Integrated Digital Effects Processing for Bass
and Treble Response
!
Digital Docking Including an I
2
S Output, 3
Synchronous I
2
S Inputs
!
Performance Oriented Digital Mixer
!
SRS
©
3D Stereo Enhancement
!
On-chip PLL for use with External Clock
Sources
!
Dedicated Microphone Analog-to-Digital
Converter
!
Sample Rate Converters
!
S/PDIF Digital Audio Output
!
AC ’97 2.1 Compliant
!
PC Beep Bypass
!
20-bit Stereo Digital-to-Analog Converters
!
18-bit Stereo Analog-to-Digital Converters
AC-LINK AND AC '97
REGISTERS
Analog Line-level Stereo Inputs for
LINE IN, VIDEO, and AUX
!
High Quality Pseudo-Differential CD Input
!
Extensive Power Management Support
!
Meets or Exceeds the Microsoft
®
PC 99 and
PC 2001 Audio Performance Requirements
Description
The CS4205 is an AC ’97 2.1 compliant stereo audio co-
dec designed for PC multimedia systems. It uses
industry leading CrystalClear
®
delta-sigma and mixed
signal technology. The CS405 is the first Cirrus AC ’97
audio codec to feature digital centric mixing and digital
effects. This advanced technology and these features
are designed to help enable the design of PC 99 and
PC 2001 compliant high-quality audio systems for desk-
top, portable, and entertainment PCs.
Coupling the CS4205 with a PCI audio accelerator or
core logic supporting the AC ’97 interface implements a
cost effective, superior quality audio solution. The
CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 au-
dio quality standards.
ORDERING INFO
CS4205-KQZ, Lead Free 48-pin TQFP 9x9x1.4 mm
ANALOG INPUT MUX
AND OUTPUT MIXER
18 bit
ADC
(2ch)
INPUT
MUX
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
ID0#
ID1#
TEST
PWR
MGT
SRC
PCM_DATA
AC-
LINK
AC
'97
REG
SRC
MIC_PCM_DATA
18 bit
ADC
(1ch)
LINE
CD
AUX
VIDEO
MIC1
MIC2
PHONE
PC_BEEP
SIGNAL
PROCESSING
ENGINE
GAIN / MUTE CONTROLS
MIXER / MUX SELECTS
INPUT
MIXER
Σ
OUTPUT
MIXER
20 bit
DAC
(2ch)
GPIO0/LRCLK
GPIO1/SDOUT
EAPD/SCLK
SPDO/SDO2
GPIO[2:4]/SDI[1:3]
ZSCLK,ZSDATA,ZLRCLK
GPIO
S/PDIF
SERIAL DATA PORT
SRC
ZV PORT
PCM_DATA
Σ
LINE_OUT
MONO_OUT
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
DS489PP4
1
CS4202
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 7
ANALOG CHARACTERISTICS ................................................................................................ 7
ABSOLUTE MAXIMUM RATINGS ...... ................ ................ ................ ............. ............. ........... 8
RECOMMENDED OPERATING CONDITIONS ....................................................................... 8
AC 97 SERIAL PORT TIMING............................................................................................... 10
2. GENERAL DESCRIPTION ..................................................................................................... 13
2.1 AC-Link ...................................................................................................................
......... 13
2.2 Control Registers .........................................................................................................
.... 14
2.3 Sample Rate Conver ters .................................................................................................. 14
2.4 Mixers ....................................................................................................................
.......... 14
2.5 Input Mux .................................................................................................................
........ 14
2.6 Volume Control ............................................................................................................
.... 14
3. AC-LINK FRAME DEFINITION .............................................................................................. 16
3.1 AC-Link Serial Data Output Frame .................................................................................. 17
3.1.1 Serial Data Output Slot Tags (Slot 0)...
.......................................................................... 17
3.1.2 Command Address Port (Slot 1) ..............
...................................................................... 17
3.1.3 Command Data Port (Slot
2).......................................................................................... 18
3.1.4 PCM Playback Data (Slots
3-4,6-11) ............................................................................. 18
3.1.5 GPIO Pin Control (Slot12).............................................................................................. 18
3.2 AC-Link Serial Data Input Frame ..................................................................................... 19
3.2.1 Serial Data Input Slot Tag Bits (Slot 0)
........................................................................ 19
3.2.2 Status Address Port (Slot 1) .......................................................................................... 19
3.2.3 Status Data Port (Slot 2) ................................................................................................
20
3.2.4 PCM Capture Data (Slot 3-4,6-8,11).............................................................................. 20
3.2.5 GPIO Pin Status (Slot 12) ............................................................................................. 20
3.3 AC-Link Protocol Violation - Loss of SYNC ..................................................................... 21
4. REGISTER INTERFACE .....................................................................................................
22
4.1 Reset Register (Index 00h) .............................................................................................. 23
4.2 Analog Mixer Output Volume Registers (Index 02h - 04h) .............................................. 23
4.3 Mono Volume Register (Index 06h) .................................................................................. 24
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sale
http://www.cirrus.com/co
rporate/contacts/sales.cfm
IMPORTANT NOTICE
s Representative contacts, visi
t the Cirrus Logic web site at:
"Preliminary" product information describes products that are in production, but for which full characterization data is not ye
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the informat
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest ve
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the t
at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No r
the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infrin
third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated
in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus inte
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purp
resale.
t available. Cirrus Logic, Inc. and its
ion is subject to change without
rsion of relevant information to
erms and conditions of sale supplied
esponsibility is assumed by Cirrus for
gement of patents or other rights of
implied under any patents, mask
with the information contained here-
grated circuits or other products of
oses, or for creating any work for
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS) . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SE-
CURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRO DUCTS IN SUCH APPLICATIONS
IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IM-
PLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURP OSE, WITH REGARD TO ANY CIRRUS
PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMERS CUSTOMER USES OR PERMITS THE USE OF CIRRUS PROD-
UCTS IN CRITICAL APPLICATIONS, CUSTOMER AG REES, BY SUCH USE, TO FULLY INDEMNIFY CI RRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES,
DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS FEES AND COSTS, THAT MAY RESULT FROM OR
ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trad
marks or service marks of their respective owners.
emarks of Cirrus Logic, Inc. All other brand and product names
in this document may be trade-
2
DS549PP2
CS4202
4.4 PC_BEEP Volume Register (I ndex 0Ah) ................. ................ ................ ................ ......... 24
4.5 Phone Volume Register (Index 0Ch) ................................................................................ 24
4.6 Microphone Volume Register (Index 0Eh)..
...................................................................... 25
4.7 Analog Mixer Input Gain Registers (Index 10h - 18h) ...................................................... 26
4.8 Input Mux Select Re gister (Index 1Ah) ............................................................................. 27
4.9 Record Gain Register (Index 1Ch) .............
...................................................................... 28
4.10 General Purpose Register
(Index 20h) ......................................................................... 29
4.11 Powerdown Control/Status Register (Index
26h) ........................................................... 30
4.12 Extended Audio ID Register (Index 28h) .
....................................................................... 31
4.13 Extended Audio Status/Con trol Register (Index 2Ah) .................................................... 32
4.14 Audio Sample Rate Control Registers (I
ndex 2Ch - 32h) ............................................... 33
4.15 S/PDIF Control Register (Index 3Ah) ............................................................................. 34
4.16 Extended Modem ID Regist er (Index 3Ch) .................................................................... 35
4.17 Extended Modem Status/Con
trol Register (Index 3Eh) ................................................. 35
4.18 GPIO Pin Configuration Register (Index
4Ch) ................................................................ 35
4.19 GPIO Pin Polarity/Type Configuration Regi ster (Index 4Eh) .......................................... 36
4.20 GPIO Pin Sticky Register (Index 50h) ............................................................................ 36
4.21 GPIO Pin Wakeup Mask Register (Index 52h) ............................................................... 37
4.22 GPIO Pin Status Register (Index 54h)............................................................................ 37
4.23 AC Mode Control Register (Index 5Eh) .......................................................................... 37
4.24 Misc. Crystal Control Register (Index 60h) ..................................................................... 39
4.25 Serial Port Control Register (Index 6Ah) ........................................................................ 40
4.26 BIOS-Driver Interface Control Registers (I ndex 70h - 72h) ............................................ 41
4.27 BIOS-Driver Interface Status Register (Index 7Ah) ........................................................ 41
4.28 Vendor ID1 Register (Index 7Ch) ................................................................................... 42
4.29 Vendor ID2 Register (Index 7Eh) ................................................................................... 42
5. SERIAL DATA PORTS .........................................................................................................
.. 43
5.1 Overview ..................................................................................................................
........ 43
5.2 Multi-Channel Expansion ................................................................................................. 43
5.3 Serial Data Formats .......................................................................................................
.. 44
6. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 45
7. EXCLUSIVE FUNCTIONS ...................................................................................................... 4
5
8. POWER MANAGEMENT ....................................................................................................... 46
8.1 AC 97 Reset Modes ........................................................................................................ 4
6
8.1.1 Cold Reset .......................................................................................................... 46
8.1.2 Warm Reset ........................................................................................................ 46
8.1.3 New Warm Reset ................................................................................................ 46
8.1.4 Register Reset .................................
................................................................... 46
8.2 Powerdown Controls ....................................................................................................... 4
7
9. CLOCKING ..................................................................................................................
........... 49
9.1 PLL Operation (External Clock) ....................................................................................... 49
9.2 24.576 MHz Crystal Operation ........................................................................................ 49
9.3 Secondary Codec Operation ........................................................................................... 49
10. ANALOG HARDWARE DESCRIPTION ............................................................................... 51
10.1 Analog Inputs ............................................................................................................
..... 51
10.1.1 Line Inputs ........................................................................................................ 51
10.1.2 CD Input ............................................................................................................ 51
10.1.3 Microphone Inputs .. .......................................................................................... 51
10.1.4 PC Beep Input ......... .......................................................................................... 52
10.1.5 Phone Input ....................................................................................................... 52
10.2 Analog Outputs ...........................................................................................................
... 52
10.2.1 Stereo Outputs ........ .......................................................................................... 52
10.2.2 Mono Output ........... .......................................................................................... 53
10.3 Miscellaneous Analog Signals .................
...................................................................... 53
DS549PP2
3
CS4202
10.4 Power Supplies ..............
.............................................................................................
... 53
. 53
... 56
64
....... 65
10.5 Reference Design .........................................................................................................
11. GROUNDING AND LAYOUT .............................................................................................. 54
12. PIN DESCRIPTIONS
14. REFERENCE DESIGN
.....................................................................................................
...................................................................................................
13. PARAMETER AND TERM DEFINITIONS ............................................................................ 62
15. REFERENCES ...............................................................................................................
16. PACKAGE DIMENSIONS ..................................................................................................... 66
LIST OF FIGURES
Figure 1. Power Up Timing............................
Figure 2. Codec Ready from Star
..........................................................................
...... 11
............. 11
.... 12
.......... 12
..... 13
. 15
t-up or Fault Condition .............................................................. 11
Figure 3. Clocks ...............................................................................................................
Figure 4. Data Setup and Hold..................................................................................................
Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 12
Figure 6. Test Mode ............................................................................................................
Figure 7. AC-link Connections..................................................................................................
Figure 8. CS4202 Mixer Diagram.................................................................................................
Figure 9. AC-link Input and Output Framing.....
Figure 10. Serial Data Port: Si
Figure 11. Serial Data Format
Figure 12. Serial Data Format
Figure 13. Serial Data Format 2
Figure 14. Serial Data Format 3
............................................................................. 16
. 44
x Channel Circuit ........................................................................... 43
0 (I2S) ..........................................................................................
1 (Left Justified) ............................................................................ 44
(Right Justified, 20-bit data) ....................................................... 44
(Right Justified, 16-bit data) ....................................................... 44
....... 45
... 49
........ 50
..........................................................................
Figure 15. S/PDIF Output.......................................................................................................
Figure 16. PLL External Loop Filter..................
Figure 18. Line Input (Replicate
Figure 17. External Crystal....................................................................................................
Figure 19. Differential 1 VRMS CD
Figure 21. PC_BEEP Inpu
for Video and AUX) .................................................................... 51
Input ...................................................................................... 51
..... 52
.. 52
Figure 20. Microphone Input .. ..................................................................................................
Figure 22. Modem Connection ....................................................................................................
Figure 23. Line Out and Headphone Out Setup............................................................................ 53
Figure 24. Line Out/Headphone Out Setup.........
Figure 25. +5V Analog Voltage Regulator...........
Figure 26. Conceptual Layout
t............... ................ ................ ................. ................ ............. .......... ..... 52
.......................................................................... 53
.......................................................................... 54
OSC Clocking Modes ............... 55
for the CS4202 when in XTAL or
Figure 27. Pin Locations for the CS4202 ...................................................................................... 56
Figure 28. CS4202 Reference Design ....................
...................................................................... 64
4
DS549PP2
FPGA/CPLD
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