2.5 V to 5.5 V, 500 A, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305/AD5315/AD5325
*
FEATURES
AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP
A Version: 1 LSB INL, B Version: 0.625 LSB INL
AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP
A Version: 4 LSB INL, B Version: 2.5 LSB INL
AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP
A Version: 16 LSB INL, B Version: 10 LSB INL
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
2-Wire (I
2
C
®
Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Three Power-Down Modes
Double-Buffered Input Logic
Output Range: 0 V to V
REF
Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40 C to +105 C
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500
µA
at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus compatible at V
DD
< 3.6 V. Multiple devices can be
placed on the same bus.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software
LDAC
function. The parts incorporate a
power-on reset circuit, which ensures that the DAC outputs power
up to 0 V and remain there until a valid write takes place to the
device. There is also a software clear function that resets all input
and DAC registers to 0 V. The parts contain a power-down
feature that reduces the current consumption of the devices to
200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1
µW
in power-down mode.
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
FUNCTIONAL BLOCK DIAGRAM
V
DD
LDAC
REF IN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
V
OUT
A
SCL
SDA
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
A0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
V
OUT
D
POWER-ON
RESET
AD5305/AD5315/AD5325
GND
POWER-DOWN
LOGIC
*Protected
by U.S.Patent No. 5,969,657and 5,684,481.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5305/AD5315/AD5325–SPECIFICATIONS
C = 200 pF to GND; all specifications T to T , unless otherwise noted.)
L
MIN
MAX
(V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 k
to GND;
Parameter
1
DC PERFORMANCE
3, 4
AD5305
Resolution
Relative Accuracy
Differential Nonlinearity
AD5315
Resolution
Relative Accuracy
Differential Nonlinearity
AD5325
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Offset Error Drift
5
Gain Error Drift
5
Power Supply Rejection Ratio
5
DC Crosstalk
5
DAC REFERENCE INPUTS
5
V
REF
Input Range
V
REF
Input Impedance
Reference Feedthrough
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
6
Maximum Output Voltage
6
DC Output Impedance
Short Circuit Current
Power-Up Time
Min
A Version
2
Typ
Max
Min
B Version
2
Typ
Max
Unit
Conditions/Comments
8
±
0.15
±
0.02
±
1
±
0.25
8
±
0.15
±
0.02
±
0.625
±
0.25
Bits
LSB
LSB
Guaranteed Monotonic by Design
over All Codes
10
±
0.5
±
0.05
±
4
±
0.5
10
±
0.5
±
0.05
±
2.5
±
0.5
Bits
LSB
LSB
Guaranteed Monotonic by Design
over All Codes
12
±
2
±
0.2
±
0.4
±
0.15
20
–12
–5
–60
200
0.25
37
±
16
±
1
±
3
±
1
60
12
±
2
±
0.2
±
0.4
±
0.15
20
–12
–5
–60
200
±
10
±
1
±
3
±
1
60
Bits
LSB
LSB
% of FSR
% of FSR
mV
Guaranteed Monotonic by Design
over All Codes
Lower deadband exists only if
offset error is negative.
ppm of FSR/°C
ppm of FSR/°C
dB
V
DD
=
±
10%
µV
R
L
= 2 kΩ to GND or V
DD
V
DD
V
kΩ
MΩ
dB
V
V
Ω
mA
mA
µs
µs
V
DD
45
>10
–90
0.001
V
DD
– 0.001
0.5
25
16
2.5
5
0.25
37
45
>10
–90
0.001
V
DD
– 0.001
0.5
25
16
2.5
5
Normal Operation
Power-Down Mode
Frequency = 10 kHz
This is a measure of the minimum
and maximum drive capability
of the output amplifier.
V
DD
= 5 V
V
DD
= 3 V
Coming out of Power-Down Mode.
V
DD
= 5 V
Coming out of Power-Down Mode.
V
DD
= 3 V
LOGIC INPUTS (A0)
5
Input Current
V
IL
, Input Low Voltage
±
1
0.8
0.6
0.5
2.4
2.1
2.0
3
0.7 V
DD
–0.3
0.05 V
DD
8
50
V
DD
+ 0.3 0.7 V
DD
0.3 V
DD
–0.3
±
1
0.05 V
DD
8
2.4
2.1
2.0
3
±
1
0.8
0.6
0.5
V
IH
, Input High Voltage
Pin Capacitance
LOGIC INPUTS (SCL, SDA)
5
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
I
IN
, Input Leakage Current
V
HYST
, Input Hysteresis
C
IN
, Input Capacitance
Glitch Rejection
LOGIC OUTPUT (SDA)
5
V
OL
, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
µA
V
V
V
V
V
V
pF
V
DD
= 5 V
±
V
DD
= 3 V
±
V
DD
= 2.5 V
V
DD
= 5 V
±
V
DD
= 3 V
±
V
DD
= 2.5 V
10%
10%
10%
10%
V
DD
+ 0.3 V
0.3 V
DD
V
±
1
µA
V
pF
50
ns
SMBus Compatible at V
DD
< 3.6 V
SMBus Compatible at V
DD
< 3.6 V
Input filtering suppresses noise
spikes of less than 50 ns.
I
SINK
= 3 mA
I
SINK
= 6 mA
0.4
0.6
±
1
8
8
0.4
0.6
±
1
V
V
µA
pF
–2–
REV. F
AD5305/AD5315/AD5325
Parameter
1
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
7
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
Min
2.5
A Version
2
Typ
Max
5.5
Min
2.5
B Version
2
Typ
Max
5.5
Unit
V
µA
µA
µA
µA
Conditions/Comments
V
IH
= V
DD
and V
IL
= GND
600
500
0.2
0.08
900
700
1
1
600
500
0.2
0.08
900
700
1
1
V
IH
= V
DD
and V
IL
= GND
I
DD
= 4
µA
(Max) During 0
Readback on SDA
I
DD
= 1.5
µA
(Max) During 0
Readback on SDA
NOTES
1
See the Terminology section.
2
Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
REF
= V
DD
and offset plus gain error must be
positive.
7
I
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Specifications subject to change without notice.
AC CHARACTERISTICS
1
otherwise noted.)
Parameter
2
Output Voltage Settling Time
AD5305
AD5315
AD5325
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
(V
DD
= 2.5 V to 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless
A, B Version
3
Min
Typ
Max
6
7
8
0.7
12
1
1
3
200
–70
8
9
10
Unit
µs
µs
µs
V/µs
nV-s
nV-s
nV-s
nV-s
kHz
dB
Conditions/Comments
V
REF
= V
DD
= 5 V
1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
1 LSB Change around Major Carry
V
REF
= 2 V
±
0.1 V p-p
V
REF
= 2.5 V
±
0.1 V p-p, Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See the Terminology section.
3
Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.
Specifications subject to change without notice.
REV. F
–3–
AD5305/AD5315/AD5325
TIMING CHARACTERISTICS
1, 2
Parameter
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6 3
t
7
t
8
t
9
t
10
t
11
Limit at T
MIN
, T
MAX
(A, B Version)
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1C
B4
400
(V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Unit
kHz max
µs
min
µs
min
µs
min
µs
min
ns min
µs
max
µs
min
µs
min
µs
min
µs
min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Conditions/Comments
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
SU,DAT
, Data Setup Time
t
HD,DAT
, Data Hold Time
t
HD,DAT
, Data Hold Time
t
SU,STA
, Setup Time for Repeated Start
t
SU,STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time between a STOP and a START Condition
t
R
, Rise Time of SCL and SDA when Receiving
t
R
, Rise Time of SCL and SDA when Receiving (CMOS Compatible)
t
F
, Fall Time of SDA when Transmitting
t
F
, Fall Time of SDA when Receiving (CMOS Compatible)
t
F
, Fall Time of SCL and SDA when Receiving
t
F
, Fall Time of SCL and SDA when Transmitting
Capacitive Load for Each Bus Line
C
B
NOTES
1
See Figure 1.
2
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Specifications subject to change without notice.
SDA
t
9
t
3
t
10
t
11
t
4
SCL
t
4
START
CONDITION
t
6
t
2
t
5
t
7
REPEATED
START
CONDITION
t
1
t
8
STOP
CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram
–4–
REV. F
AD5305/AD5315/AD5325
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
A0 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
A–D to GND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Version) . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . . 150°C
MSOP
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max – T
A
)/
JA
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model
AD5305ARM
AD5305ARM-REEL7
AD5315ARM
AD5315ARM-REEL7
AD5325ARM
AD5325ARM-REEL7
AD5305BRM
AD5305BRM-REEL
AD5305BRM-REEL7
AD5315BRM
AD5315BRM-REEL
AD5315BRM-REEL7
AD5325BRM
AD5325BRM-REEL
AD5325BRM-REEL7
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
DEA
DEA
DFA
DFA
DGA
DGA
DEB
DEB
DEB
DFB
DFB
DFB
DGB
DGB
DGB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5305/AD5315/AD5325 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. F
–5–
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