CS4923/4/5/6/7/8/9
Multi-Channel Digital Audio Decoders
l
CS4923/4/5/6/7/8
features
Description
The CS4923/4/5/6/7/8 is a family of multi-channel digital
audio decoders, with the exception of the CS4929 as the
only stereo digital audio decoder. The CS4923/4/5/6 are
designed for Dolby Digital and MPEG-2 Stereo decoding. In
addition the CS4925 adds MPEG-2 multi-channel decoding
capability and the CS4926 provides DTS decoding. The
CS4927 is an MPEG-2 multi-channel decoder and the
CS4928 is a DTS multi-channel decoder. The CS4929 is an
AAC 2-channel and MPEG-2 stereo decoder. Each one of
the CS4923/4/5/6/7/8/9 provides a complete and flexible
solution for multi-channel (or stereo in the case of the
CS4929) audio decoding in home A/V receiver/amplifiers,
DVD movie players, out-board decoders, laser-disc players,
HDTV sets, head-end decoders, set-top boxes, and similar
products.
Cirrus Logic’s Crystal Audio Division provides a complete set
of audio decoder and auxiliary audio DSP application
programs for various applications. For all complementary
analog and digital audio I/O, Crystal Audio also provides a
complete set of high-quality audio peripherals including:
multimedia CODECs, stereo A/D and D/A converters and
IEC60958 interfaces. Of special note, the CS4226 is a
complementary CODEC providing a digital receiver, stereo
A/D converters, and six 20-bit DACs in one package.
ORDERING INFORMATION
CS4923xx-CL 44-pin PLCC (xx = ROM revision)
CRD4923
Reference design with CS4226
CDB4923
Evaluation board
— Optional Virtual 3D Output
— Simulated Surround and Programmable Effects
— Real Time Autodetection of Dolby Digital
®
,
DTS
®
, MPEG Multi-Channel and PCM
— Flexible 6-channel master or slave output
l
CS4923/4/5/6/7/8/9
features
— IEC60958/61937 transmitter for compressed-
data or linear-PCM output
— Dedicated 8 kilobyte input buffer
— DAC clock via analog phase-locked loop
— Dedicated byte wide or serial host interface
— Multiple compressed data input modes
— PES layer decode for A/V synchronization
— 96-kHz-capable PCM I/O, master or slave
— Optional external memory and auto-boot
— +3.3-V CMOS low-power, 44-pin package
l
CS4923/4/5/6
features
— Capable of Dolby Digital
®
Group A Performance
— Dolby bass manager and crossover filters
— Dolby Surround Pro Logic
®
Decoding
l
CS4925/7:
MPEG-2 Multi-Channel Decoder
l
CS4926/8: DTS Multi-Channel Decoder
l
CS4929: AAC 2-Channel (Low Complexity)
and MPEG-2 Stereo Decoder
RESET
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
RD,
WR,
SCDIO,
DATA7:0,
R/W,
DS,
SCDOUT,
EMAD7:0,
EMOE, EMWR,
PSEL, A0,
A1,
ABOOT,
GPIO7:0
CS
GPIO11 GPIO10 GPIO9 SCCLK SCDIN
INTREQ
EXTMEM,
GPIO8
DD
DC
Compressed
Data Input
Interface
Parallel or Serial Host Interface
Framer
Shifter
Input
Buffer
Controller
24-Bit
DSP Processing
RAM
RAM
Program Data
Memory Memory
ROM
ROM
Program Data
Memory Memory
STC
Output
Formatter
MCLK
SCLK
LRCLK
AUDATA[2.0]
RAM
Output
Buffer
Digital
Audio
Input
Interface
RAM Input
Buffer
PLL
Clock Manager
FILT2 FILT1
VA AGND
XMT958
DGND[3:1]
VD[3:1]
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 1999
(All Rights Reserved)
AUG ‘99
DS262F2
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CS4923/4/5/6/7/8/9
TABLE OF CONTENTS
1.
CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
ABSOLUTE MAXIMUM RATINGS ............................................................................................ 4
RECOMMENDED OPERATING CONDITIONS ........................................................................ 4
DIGITAL D.C. CHARACTERISTICS .......................................................................................... 4
POWER SUPPLY CHARACTERISTICS ................................................................................... 4
SWITCHING CHARACTERISTICS—RESET ............................................................................ 5
SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK........................................................ 6
SWITCHING CHARACTERISTICS—CLKIN ............................................................................. 7
SWITCHING CHARACTERISTICS—INTEL
®
HOST MODE..................................................... 8
SWITCHING CHARACTERISTICS—MOTOROLA
®
HOST MODE ........................................ 10
SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT................................................ 16
SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT............................................ 18
FAMILY OVERVIEW .............................................................................................................. 20
2.1 Multi-channel Decoder Family of Parts ............................................................................ 21
2.2 Document Strategy .......................................................................................................... 21
2.2.1
Hardware Documentation ............................................................................... 22
2.2.2
CS4923/4/5/6/7/8/9 Application Code User’s Guides ..................................... 22
2.3 Using the CS4923/4/5/6/7/8/9 .......................................................................................... 22
TYPICAL CONNECTION DIAGRAMS ................................................................................... 23
3.1 Multiplexed Pins ............................................................................................................... 23
3.2 Termination Requirements ............................................................................................... 24
3.3 Phase Locked Loop Filter ................................................................................................ 24
POWER .................................................................................................................................. 31
4.1 Decoupling ....................................................................................................................... 31
4.2 Analog Power Conditioning .............................................................................................. 31
4.3 Pads ................................................................................................................................. 31
CLOCKING ............................................................................................................................. 32
CONTROL .............................................................................................................................. 33
6.1 Boot and Control Mode Overview .................................................................................... 33
6.2 Parallel Host Interface ...................................................................................................... 34
6.2.1
Intel Parallel Host Mode .................................................................................. 34
6.2.2
Motorola Parallel Host Mode ........................................................................... 36
6.3 SPI Serial Host Interface .................................................................................................. 36
6.3.1
SPI Write ......................................................................................................... 37
6.3.2
SPI Read ......................................................................................................... 37
2.
3.
4.
5.
6.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Dolby, Dolby Digital, and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation.
Intel is a registered trademark of Intel Corporation.
Motorola is a registered trademark of Motorola, Inc.
I
2
C is a registered trademark of Philips Semiconductor.
All other names are trademarks, registered trademarks, or service marks of their respective companies.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
2
DS262F2
CS4923/4/5/6/7/8/9
6.4 I
2
C Serial Host Interface .................................................................................................. 39
6.4.1
I
2
C Write ......................................................................................................... 39
6.4.2
I
2
C Read ......................................................................................................... 39
6.5 External Memory .............................................................................................................. 41
6.5.1
External Memory and Autoboot ...................................................................... 43
DIGITAL INPUT & OUTPUT .................................................................................................. 44
7.1 Digital Audio Formats ....................................................................................................... 44
7.2 Digital Audio Input Port .................................................................................................... 46
7.3 Compressed Data Input Port ........................................................................................... 46
7.4 Parallel Digital Audio Data Input ...................................................................................... 46
7.5 Digital Audio Output Port ................................................................................................. 47
7.5.1
IEC60958 Output ............................................................................................ 48
PIN DESCRIPTIONS .............................................................................................................. 49
PACKAGE DIMENSIONS ...................................................................................................... 54
7.
8.
9.
LIST OF FIGURES
Figure 1.
RESET
Timing .................................................................................................................. 5
Figure 2. Serial Compressed Data Timing ....................................................................................... 6
Figure 3. CLKIN with CLKSEL = VSS = PLL Enable........................................................................ 7
Figure 4. CLKIN with CLKSEL = VD = PLL Bypass ......................................................................... 7
Figure 5. Intel Parallel Host Mode Read Cycle................................................................................. 9
Figure 6. Intel Parallel Host Mode Write Cycle................................................................................. 9
Figure 7. Motorola Parallel Host Mode Read Cycle ....................................................................... 11
Figure 8. Motorola Parallel Host Mode Write Cycle........................................................................ 11
Figure 9. SPI Control Port Timing................................................................................................... 13
Figure 10. I
2
C Control Port Timing ................................................................................................. 15
Figure 11. Digital Audio Input, Data and Clock Timing................................................................... 17
Figure 12. Digital Audio Output, Data and Clock Timing ................................................................ 19
Figure 13. I
2
C Control..................................................................................................................... 25
Figure 14. I
2
C Control with External Memory ................................................................................. 26
Figure 15. SPI Control .................................................................................................................... 27
Figure 16. SPI Control with External Memory ................................................................................ 28
Figure 17. Intel Parallel Control Mode ............................................................................................ 29
Figure 18. Motorola Parallel Control Mode..................................................................................... 30
Figure 19. SPI Timing..................................................................................................................... 38
Figure 20. I
2
C Timing ..................................................................................................................... 40
Figure 21. External Memory Interface ............................................................................................ 42
Figure 22. Run-Time Memory Access ............................................................................................ 42
Figure 23. Autoboot Timing Diagram.............................................................................................. 43
Figure 24. I
2
S Format ..................................................................................................................... 45
Figure 25. Left Justified Format...................................................................................................... 45
Figure 26. Right Justified................................................................................................................ 45
Figure 27. Multi-Channel Format (M == 20) ................................................................................... 45
LIST OF TABLES
Table 1. Silicon Revisions .............................................................................................................. 20
Table 2. Host Modes ...................................................................................................................... 33
Table 3. Host Memory Map ............................................................................................................ 34
Table 4. Intel Parallel Host Mode Pin Assignments........................................................................ 34
Table 5. Parallel Input/Output Registers......................................................................................... 35
Table 6. Motorola Parallel Host Mode Pin Assignments ................................................................ 36
Table 7. SPI Serial Mode Pin Assignments.................................................................................... 36
Table 8. I
2
C Serial Mode Pin Assignments .................................................................................... 39
Table 9. Memory Interface Pins...................................................................................................... 41
Table 10. Digital Audio Input Port................................................................................................... 46
Table 11. Compressed Data Input Port .......................................................................................... 46
Table 12. Digital Audio Output Port ................................................................................................ 47
Table 13. MCLK/SCLK Master Mode Ratios .................................................................................. 47
DS262F2
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CS4923/4/5/6/7/8/9
1.
CHARACTERISTICS AND SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0 V; all voltages with respect to 0 V)
Parameter
DC power supplies:
Positive digital
Positive analog
||VA| – |VD||
Symbol
VD
VA
I
in
V
IND
T
Amax
T
stg
Min
–0.3
–0.3
-
-
–0.3
–55
–65
Max
3.63
3.63
0.4
±10
5.5
125
150
Unit
V
V
V
mA
V
°C
°C
Input current, any pin except supplies
Digital input voltage
Ambient operating temperature (power applied)
Storage temperature
WARNING:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0 V; all voltages with respect to 0 V)
Parameter
DC power supplies:
Positive digital
Positive analog
||VA| – |VD||
Symbol
VD
VA
T
A
Min
3.13
3.13
-
0
Typ
3.3
3.3
-
-
Max
3.47
3.47
0.4
70
Unit
V
V
V
°C
Ambient operating temperature
DIGITAL D.C. CHARACTERISTICS
(T
A
= 25
°C;
VA, VD[3:1] = 3.3 V
±5%;
measurements performed under static conditions.)
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage at I
O
= –4.0 mA
Low-level output voltage at I
O
= 4.0 mA
Input leakage current
Symbol
V
IH
V
IL
V
OH
V
OL
I
in
Min
2.0
-
VD
×
0.9
-
-
Typ
-
-
-
-
-
Max
-
0.8
-
VD
×
0.1
1.0
Unit
V
V
V
V
µA
POWER SUPPLY CHARACTERISTICS
(T
A
= 25
°C;
VA, VD[3:1] = 3.3 V
±5%;
measurements performed under operating conditions)
Parameter
Power supply current:
Digital operating: VD[3:1]
Analog operating: VA
Symbol
Min
-
-
Typ
225
4
Max
435
8
Unit
mA
mA
4
DS262F2
CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS—RESET
(T
A
= 25
°C;
VA, VD = 3.3 V
±5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)z
Parameter
RESET minimum pulse width low
All bidirectional pins high-Z after RESET low
Configuration bits setup before RESET high
Configuration bits hold after RESET high
Symbol
T
rstl
T
rst2z
T
rstsu
T
rsthld
Min
100
-
50
15
Max
-
50
-
-
Unit
ns
ns
ns
ns
RESET
RD, WR,
PSEL, ABOOT
All Bidirectional
Outputs
T
rst2z
T
rstl
T
rstsu
T
rsthld
Figure 1.
RESET
Timing
DS262F2
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