Above ratings are based on the thermal resistances using a multi-layer circuit board (EIA/JESD51). For mounting on a mono-layer board, power derating shall be
needed. Please inquire of us about conditions.
※1 素子毎の負荷電力の合計が、パッケージ定格電力を超えない条件で御½用ください。
※1 Total power consumption of all elements should not exceed the package power rating.
The resistor of this product is formed by narrow patterning a thin metal film. Thus, application of excessive voltage causes burn and destruction of the resistive film, abnormality
in resistance or open resistance and loss of proper function. The properly and electrostatically measured taping materials are used for the components, but attention should be paid
to the fact that there is some danger the parts may be destructed by static electricity(equivalent to 500V or over at 100pF, 1.5kΩ) to cause a change in resistance in the conditions
of an excessive dryness when mounting on the boards. Similarly, care should be given not to apply the excessive static electricity at the time of mounting on the boards. When
designing, consideration can be taken into withstanding ESD for customized KPC products. Please consult with us about the details.
●
Hand soldering by iron soldering or repairment are not recommended because KPC is a multi-pin product.
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Avoid storing components under direct sun rays, high temperature/humidity. Direct sun rays will cause quality change of taping and difficulty of keeping appropriate peeling
strength. In the case of 5〜35℃/35〜75%RH, there is no deterioration of solderability for 12 months, but take special care for storing, because condensation, dust, and toxic gas
like hydrogen sulfide, sulfurous acid gas, hydrogen chloride, etc. may drop solderability.
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introduction
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Introduction
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FPGA/CPLD
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