Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350ATS
1
1.1
FEATURES
General
•
2.7 to 3.6 V power supply
•
Integrated digital filter and Digital-to-Analog Converter
(DAC)
•
256f
s
system clock output
•
20-bit data path in interpolator
•
High performance
•
No analog post filtering required for DAC.
1.2
Control
2
APPLICATIONS
•
Digital audio systems.
3
GENERAL DESCRIPTION
•
Controlled either by means of static pins or via the
L3 microcontroller interface.
1.3
IEC 958 input
Available in two versions:
•
UDA1350ATS:
– only IEC 958 input to DAC in SSOP28 package.
•
UDA1350AH:
– full featured version in QFP44 package.
The UDA1350ATS is a single chip IEC 958 audio decoder
with an integrated stereo digital-to-analog converter
employing bitstream conversion techniques.
A lock indication signal is available on pin LOCK indicating
that the IEC 958 decoder is locked. This pin is also used to
indicate whether PCM data is applied to the input or not.
In the event non-PCM data has been detected, the device
indicates out-of-lock.
By default the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overruled in the L3 control mode.
•
On-chip amplifier for converting IEC 958 input to CMOS
levels
•
Lock indication signal available on pin LOCK
•
Lock indication signal combined on-chip with the Pulse
Code Modulation (PCM) status bit; in case non-PCM
has been detected pin LOCK indicates out-of-lock
•
Key channel-status bits available via L3 interface (lock,
pre-emphasis, audio sample frequency, two channel
PCM indication and clock accuracy).
1.4
Digital sound processing and DAC
•
Automatic de-emphasis when using IEC 958 input with
32.0, 44.1 and 48.0 kHz audio sample frequencies
•
Soft mute by means of a cosine roll-off circuit selectable
via pin MUTE or the L3 interface
•
dB linear volume control with 1 dB steps from 0 dB to
−60
dB and
−∞
dB
•
Bass boost and treble control in L3 control mode
•
Interpolating filter (f
s
to 128f
s
) by means of a cascade of
a recursive filter and a FIR filter
•
Third order noise shaper operating at 128f
s
generates
the bitstream for the DAC
•
Filter stream digital-to-analog converter.
2000 Mar 29
3
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
4
QUICK REFERENCE DATA
SYMBOL
Supplies
V
DDD
V
DDA
I
DDA(DAC)
I
DDA(PLL)
I
DDD
I
DDD(C)
P
General
t
rst
T
amb
V
o(rms)
(THD + N)/S
reset active time
ambient temperature
−
−40
note 1
f
i
= 1.0 kHz tone
at 0 dB
at
−40
dB; A-weighted
f
i
= 1.0 kHz tone;
code = 0; A-weighted
f
i
= 1.0 kHz tone
f
i
= 1.0 kHz tone
−
−
95
−
−
−
digital supply voltage
analog supply voltage
analog supply current of DAC
analog supply current of PLL
digital supply current
digital supply current of core
power consumption
DAC in playback mode
DAC in Power-down mode
power-on
power-down
2.7
2.7
−
−
−
−
−
−
−
PARAMETER
CONDITIONS
MIN.
UDA1350ATS
TYP.
MAX.
UNIT
3.0
3.0
8.0
750
0.7
2.0
16.0
80
58
3.6
3.6
−
−
−
−
−
−
−
−
+85
−
−85
−55
−
−
0.4
V
V
mA
µA
mA
mA
mA
mW
mW
µs
°C
mV
dB
dB
dB
dB
dB
250
−
900
−90
−60
100
96
0.1
Digital-to-analog converter
output voltage (RMS value)
total harmonic
distortion-plus-noise to signal
ratio
signal-to-noise ratio
channel separation
unbalance of output voltages
S/N
α
cs
∆V
o
Note
1. The output voltage of the DAC is proportional to the DAC power supply voltage.
5
ORDERING INFORMATION
TYPE
NUMBER
UDA1350ATS
PACKAGE
NAME
SSOP28
DESCRIPTION
plastic shrink small outline package; 28 leads
VERSION
SOT341-1
2000 Mar 29
4
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