ISM75-33B9K2-155.520 datasheet, PDF

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ISM75-33B9K2-155.520: DescriptionLVPECL Output Clock Oscillator,; CategoryPassive components oscillator; File Size118KB，3 Pages; ManufacturerILSI; Websitehttp://www.ilsiamerica.com

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ISM75-33B9K2-155.520 Overview

LVPECL Output Clock Oscillator,

ISM75-33B9K2-155.520 Parametric

Parameter Name	Attribute value
Objectid	7019794631
Reach Compliance Code	compliant
Other features	ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR, 7/10 INCH
maximum descent time	0.8 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
Installation features	SURFACE MOUNT
Nominal operating frequency	155.52 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Oscillator type	LVPECL
Output load	50 OHM
physical size	3.2mm x 2.5mm x 1.0mm
longest rise time	0.8 ns
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %

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3.2 mm x 2.5 mm Ceramic Low Noise SMD Oscillator,

LVCMOS / LVPECL / LVDS

ISM75 Series

Product Features

Small Surface Mount Package

Fast Sample Delivery

Pb Free/ RoHS Compliant

Leadfree Processing

Applications

xDSL

Broadcast Video

Wireless Base Stations

Sonet /SDH

WiMAX/WLAN

Server and Storage

Ethernet/LAN/WAN

Optical modules

Clock and data recovery

FPGA/ASIC

Backplanes

GPON

3.20±0.10

Marking

2.50±0.10

1.00±0.15

Frequency

LVCMOS

LVPECL

LVDS

Output Level

LVCMOS

LVPECL

LVDS

Duty Cycle

LVCMOS

LVPECL

LVDS

Rise / Fall Time

LVCMOS

LVPECL

LVDS

Output Load

LVCMOS

LVPECL

LVDS

Frequency Stability

Supply Voltage (Vcc)

Aging

Current

10.000MHz to 250.000MHz

10.000MHz to 1500.000MHz

Logic “0” = 10% of Vcc min, Logic “1” = 90% of Vcc max

Logic “0”= Vcc-1.62V max., Logic “1” = 1.02 V min

VOD=(Diff. Output) 350mV Typ.

50% ±5% @ 50% of Vcc

50% ±5% @ 50%*

2.0 ns max. (10% to 90%)*

0.8 ns max. (20% to 80%)*

15pF



to Vcc - 2.0 VDC

RL=100

/CL=

5pF

See Table Below

+3.30 VDC ± 5%, +2.50 VDC ± 5%

±3.0 ppm max per year

HCMOS = 45 mA max

LVPECL = 90 mA max

LVDS = 35 mA max

0.5 ps typical

See Table Below

-40



C to +85



.60

TYP

1.30

TYP

1.60

2.30

.70

1.80

.90

.80

Suggested Land Pattern

PIN CONNECTIONS

PIN 1

PIN 2

PIN 3

PIN 4

PIN 5

PIN 6

Enable/Disable

or N/C

Enable/Disable

or N/C

Ground

Output

Comp. Output

or N/C

Voltage Supply

.90

Phase Jitter (RMS)

At (12kHz to 20MHz)

Operating Temp. Range

Storage Temp. Range

Dimension Units: mm

Part Number Guide

Package

Input

Voltage

3 = 3.3V

6 = 2.5V

Sample Part Number:

Operating

Temperature

1 = 0 C to +70 C

2 = -40 C to +85 C

3 = -20 C to +70 C

ISM75–31A9H2–155.520

Output

3 = LVCMOS

8 = LVDS

9 = LVPECL

Stability

(in ppm)

F =

20

A =

25

B =

50

Enable / Disable

H = Enable (Pin 1)

K = Enable (Pin 2)

Complimentary

Ouput (Pin 5) **

1 = N.C.

2 = Output

Frequency

ISM75

-155.520 MHz

NOTE: A 0.01 µF bypass capacitor is recommended between V

(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of

waveform. ** Available on LVDS and LVPECL ouput only

ILSI America Phone 775-851-8880

●

Fax 775-851-8882

●email:

e-mail@ilsiamerica.com

●

www.ilsiamerica.com

Specifications subject to change without notice

Rev: 03/10/15_A

Page 1 of 3

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