'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR
-70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V208 is 2,097,152-bit CMOS static RAM organized as
262,144-words by 8-bit which is fabricated using high-performance
quadruple-polysilicon and double metal CMOS technology. The use
of thin film transistor(TFT) load cells and CMOS periphery results in a
high density and low power static RAM. The M5M5V208 is designed
for memory applications where high reliability, large storage, simple
interfacing and battery back-up are important design objectives.
The M5M5V208VP,RV,KV,KR are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD).Two types of devices are available.
VP,KV(normal lead bend type package),RV,KR(reverse lead bend
type package). Using both types of devices, it becomes very easy to
design a printed circuit board.
PIN CONFIGURATION (TOP VIEW)
A
17 1
A
16 2
A
14 3
A
12 4
A
7 5
A
6 6
A
5 7
A
4 8
A
3 9
A
2 10
A
1 11
A
0 12
DQ
1 13
DQ
2 14
DQ
3 15
(0V)
GND
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FEATURE
Type
M5M5V208FP,VP,RV,KV,KR-70L
M5M5V208FP,VP,RV,KV,KR-85L
M5M5V208FP,VP,RV,KV,KR-10L
M5M5V208FP,VP,RV,KV,KR-12L
M5M5V208FP,VP,RV,KV,KR-70LL
M5M5V208FP,VP,RV,KV,KR-85LL
M5M5V208FP,VP,RV,KV,KR-10LL
M5M5V208FP,VP,RV,KV,KR-12LL
Access Power supply current
time
Active Stand-by
(max)
(max)
(max)
70ns
85ns
100ns
120ns
70ns
85ns
100ns
120ns
27mA
(Vcc=3.6V)
V
CC
(3V)
A
15
S
2
W
A
13
A
8
A
9
A
11
OE
A
10
S
1
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
Outline 32P2M-A(FP)
60µA
(Vcc=3.6V)
10µ A
(Vcc=3.6V)
• Single 2.7 ~ 3.6V power supply
• Operating temperature of 0 to +70°C
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S1 & S2
• Data retention supply voltage=2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Small stand-by current · · · · · · · · · · 0.3µA(typ.)
A
11
A
9
A
8
A
13
W
S
2
A
15
Vcc
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
M5M5V208VP,KV
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
S
1
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A
0
A
1
A
2
A
3
Outline 32P3H-E(VP), 32P3K-B(KV)
PACKAGE
M5M5V208FP
: 32 pin 525 mil SOP
M5M5V208VP,RV : 32pin 8 X 20 mm2
TSOP
M5M5V208KV,KR : 32pin 8 X 13.4 mm2 TSOP
S
2
W
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
Vcc
A
15
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
M5M5V208RV,KR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
3
A
2
A
1
A
0
DQ1
DQ2
DQ3
GND
DQ4
DQ5
DQ6
DQ7
DQ8
S
1
A
10
OE
APPLICATION
Small capacity memory units
Battery operating system
Handheld communiation tools
Outline 32P3H-F(RV), 32P3K-C(KR)
MITSUBISHI
ELECTRIC
1
'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR
-70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208 is determined by a
combination of the device control inputs S
1
, S
2
, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S
1
and the high level S
2
. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, S
1
or S
2
, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained. The output enable OE directly controls the
output stage. Setting the OE at a high level,the output stage
is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and
OE at a low level while S
1
and S
2
are in an active state (S
1
= L ,S
2
= H).
When setting S
1
at a high level or S
2
at a low level, the
chips are in a non-selectable mode in which both reading
and writing are disabled. In this mode, the output stage is in
a high-impedance state, allowing OR-tie with other chips
and memory expansion by S
1
or S
2
. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
FUNCTION TABLE
S
1
X
H
L
L
L
S
2
L
X
H
H
H
W
X
X
L
H
H
OE
X
X
X
L
H
Mode
Non selection
Non selection
Write
Read
DQ
High-impedance
High-impedance
D
IN
D
OUT
High-impedance
Icc
Standby
Standby
Active
Active
Active
BLOCK DIAGRAM
*
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
A
15
8
7
6
5
4
3
2
1
31
16
15
14
13
12
11
10
9
7
262144 WORDS
X 8 BITS
512 ROWS
X 128 COLUMNS
X 32 BLOCKS
21
22
23
25
26
27
28
29
13
14
15
17
18
19
20
21
*
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
A
0
A
1
A
2
A
3
A
10
A
11
A
9
A
8
A
13
12
11
10
9
23
25
26
27
28
20
19
18
17
5
31
30
1
6
2
32
3
4
8
32
24
30
22
29
CLOCK
GENERATOR
W
S
1
S
2
OE
V
CC
(3V)
24
16
GND
(0V)
*Pin numbers inside dotted line show those of TSOP.
MITSUBISHI
ELECTRIC
2
'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR
-70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Vcc
V
I
V
O
Pd
Topr
Tstr
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to GND
Ta=25°C
Ratings
– 0.5
*
~4.6
– 0.5
*
~ Vcc + 0.5
(Max 4.6)
Unit
V
V
V
mW
°C
°C
0 ~ Vcc
700
0 ~ 70
– 65 ~150
* –3.0V in case of AC ( Pulse width
≤
30ns )
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input current
Output current in off-state
Active supply current
(CMOS-level Input)
(Ta=0~70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Test conditions
Limits
Min
2.0
Typ
Max
Vcc
+0.3V
0.6
Unit
V
V
V
V
I
OH
= –0.5mA
I
OH
= –0.05mA
I
OL
=2mA
V
I
=0
~
Vcc
S
1
=V
IH
or S
2
=V
IL
or OE=V
IH
V
I/O
=0
~
Vcc
S
1
≤
0.2V, S
2
≥
Vcc-0.2V
,
o
ther inputs
≤
0.2V
or
≥
Vcc-0.2V,output-open
S
1
=V
IL
,S
2
=V
IH
,
o
ther inputs=V
IH
or V
IL
output-open
1) S
2
≤
0.2V or
–0.3*
2.4
Vcc
-0.5V
0.4
±1
±1
f= 10MHz
f= 5MHz
f= 10MHz
f= 5MHz
V
µA
µA
mA
Icc
1
20
10
22
12
25
13
27
15
60
10
1
Icc
2
Active supply current
(TTL-level Input)
mA
-L
-20 ~ +70°C
Icc
3
Stand-by current
-20 ~ +70°C
2) S
1
≥
Vcc-0.2V,
S
2
≥
Vcc-0.2V
-LL
-20 ~ +40°C
other inputs=0 ~ Vcc
+25°C
µA
0.3
0.6
0.33
mA
Icc
4
Stand-by current
S
1
=V
IH
or S
2
=V
IL
,other inputs=0
~
Vcc
* –3.0V in case of AC ( Pulse width
≤
30ns )
CAPACITANCE
Symbol
C
I
C
O
Parameter
Input capacitance
Output capacitance
(Ta=0 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Limits
Test conditions
Unit
Typ
Min
Max
pF
V
I
=GND, V
I
=25mVrms, f=1MHz
7
pF
V
O
=GND,V
O
=25mVrms, f=1MHz
9
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is for Vcc = 3V, Ta = 25°C
MITSUBISHI
ELECTRIC
3
'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR
-70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) MEASUREMENT CONDITIONS
.................................
Vcc
Input pulse level
.............
Input rise and fall time
.....
Reference level
...............
Output loads
...................
(Ta =0 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted )
1TTL
DQ
CL
including
scope and JIG
Fig.1 Output load
2.7 ~ 3.6V
V
IH
=2.2V,V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
(2) READ CYCLE
Symbol
t
CR
t
a
(A)
t
a
(S
1
)
t
a
(S
2
)
t
a
(OE)
t
dis
(S
1
)
t
dis
(S
2
)
t
dis
(OE)
t
en
(S
1
)
t
en
(S
2
)
t
en
(OE)
t
V
(A)
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
-70L,LL
Min Max
70
70
70
70
35
25
25
25
10
10
5
10
Limits
-85L,LL
-10L,LL
Min Max Min Max
85
100
85
100
85
100
85
100
45
50
30
35
30
35
30
35
10
10
10
10
5
5
10
10
-12L,LL
Min Max
120
120
120
120
60
40
40
40
10
10
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
-70L,LL
Min Max
t
CW
Write cycle time
70
t
w
(W)
Write pulse width
55
t
su
(A)
Address setup time
0
t
su
(A-WH)
Address setup time with respect to W 65
t
su
(S
1
)
Chip select 1 setup time
65
t
su
(S
2
)
Chip select 2 setup time
65
t
su
(D)
Data setup time
30
t
h
(D)
Data hold time
0
t
rec
(W)
Write recovery time
0
t
dis
(W)
25
Output disable time from W low
t
dis
(OE)
Output disable time from OE high
25
t
en
(W)
Output enable time from W high
5
t
en
(OE)
5
Output enable time from OE low
Symbol
Parameter
Limits
-85L,LL
-10L,LL
Min Max Min Max
85
100
60
75
0
0
70
85
70
85
70
85
35
40
0
0
0
0
30
35
30
35
5
5
5
5
-12L,LL
Min Max
120
85
0
100
100
100
45
0
0
40
40
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI
ELECTRIC
4
'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR
-70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
A
0~17
t
a
(A)
t
a
(S1)
S
1
(Note 3)
t
CR
t
v
(A)
t
dis
(S1)
(Note 3)
S
2
(Note 3)
t
a
(S2)
t
a
(OE)
t
en
(OE)
t
dis
(S2)
(Note 3)
OE
(Note 3)
t
dis
(OE)
t
en
(S1)
t
en
(S2)
(Note 3)
DQ
1~8
W = "H" level
DATA VALID
Write cycle (W control mode)
A
0~17
t
CW
t
su
(S1)
S
1
(Note 3)
(Note 3)
S
2
(Note 3)
t
su
(S2)
(Note 3)
t
su
(A-WH)
OE
t
su
(A)
W
t
dis
(W)
t
dis
(OE)
DQ
1~8
t
en
(W)
t
en
(OE)
t
w
(W)
t
rec
(W)
DATA IN
STABLE
t
su
(D)
MITSUBISHI
ELECTRIC
t
h
(D)
5
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