INTEGRATED CIRCUITS
DATA SHEET
UDA1360TS
Low-voltage low-power stereo
audio ADC
Preliminary specification
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC01
2000 Feb 08
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
FEATURES
General
•
Low power consumption
•
2.4 to 3.6 V power supply
•
Supports 256 and 384f
s
system clock
•
Supports sampling frequency range of 5 to 55 kHz
•
Small package size (SSOP16)
•
Integrated high-pass filter to cancel DC offset
•
Power-down mode
•
Supports 2 V (RMS) input signals
•
Easy application
•
Non-inverting ADC plus decimation filter.
Multiple format output interface
•
I
2
S-bus and MSB-justified format compatible
•
Up to 20 significant bits serial output.
Advanced audio configuration
•
Stereo single-ended input configuration
•
High linearity, dynamic range and low distortion.
QUICK REFERENCE DATA
SYMBOL
Supplies
V
DDA
V
DDD
I
DDA
I
DDD
T
amb
ADC
V
i(rms)
(THD + N)/S
S/N
α
cs
input voltage (RMS value)
total harmonic distortion plus
noise-to-signal ratio
signal-to-noise ratio
channel separation
see Table 1
at 0 dB
at
−60
dB; A-weighted
V
I
= 0 V; A-weighted
−
−
−
−
−
1.0
−85
−37
97
100
analog supply voltage
digital supply voltage
analog supply current
digital supply current
operating ambient temperature
2.4
2.4
−
−
−40
3.0
3.0
9
3.5
−
PARAMETER
CONDITIONS
MIN.
TYP.
GENERAL DESCRIPTION
UDA1360TS
The UDA1360TS is a single chip stereo Analog-to-Digital
Converter (ADC) employing bitstream conversion
techniques. The low power consumption and low voltage
requirements make the device eminently suitable for use
in low-voltage low-power portable digital audio equipment
which incorporates recording functions.
The UDA1360TS supports the I
2
S-bus data format and the
MSB-justified data format with word lengths of up to
20 bits.
MAX.
UNIT
3.6
3.6
−
−
+85
−
−80
−33
−
−
V
V
mA
mA
°C
V
dB
dB
dB
dB
ORDERING INFORMATION
TYPE
NUMBER
UDA1360TS
2000 Feb 08
PACKAGE
NAME
SSOP16
DESCRIPTION
plastic shrink small outline package; 16 leads; body width 4.4 mm
2
VERSION
SOT369-1
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
BLOCK DIAGRAM
UDA1360TS
handbook, full pagewidth
VDDA
16
VSSA
15
Vref(p) Vref(n)
5
4
Vref
2
UDA1360TS
1
ADC
(Σ∆)
8
DECIMATION
FILTER
3
ADC
(Σ∆)
CLOCK
CONTROL
14
7
SYSCLK
FSEL
PWON
VINL
VINR
DATAO
BCK
WS
13
11
12
DIGITAL
INTERFACE
DC-CANCELLATION
FILTER
9
10
VDDD
VSSD
6
MGM967
SFOR
Fig.1 Block diagram.
2000 Feb 08
3
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
PINNING
SYMBOL
VINL
V
ref
VINR
V
ref(n)
V
ref(p)
SFOR
PWON
SYSCLK
V
DDD
V
SSD
BCK
WS
DATAO
FSEL
V
SSA
V
DDA
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DESCRIPTION
left channel input
reference voltage
right channel input
ADC negative reference voltage
ADC positive reference voltage
data format selection input
power control input
system clock input 256 or 384f
s
digital supply voltage
digital ground
bit clock input
word selection input
data output
system clock frequency select
analog ground
analog supply voltage
handbook, halfpage
UDA1360TS
VINL 1
Vref 2
VINR 3
Vref(n) 4
16 VDDA
15 VSSA
14 FSEL
13 DATAO
UDA1360TS
Vref(p) 5
SFOR 6
PWON 7
SYSCLK 8
MGM968
12 WS
11 BCK
10 VSSD
9
VDDD
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
System clock
The UDA1360TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable via the static FSEL pin, and the system clock
must be locked in frequency to the digital interface input
signals.
The options are 256f
s
(FSEL = LOW) and 384f
s
(FSEL = HIGH). The sampling frequency range is
5 to 55 kHz.
The BCK clock can be up to 128f
s
, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: f
BCK
≤
128
×
f
WS
.
Notes:
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface.
2. For MSB justified formats it is important to have a WS
signal with 50% duty factor.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1360TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
Input level
The overall system gain is proportional to V
DDA
. The 0 dB
input level is defined as that which gives a
−1
dB FS digital
output (relative to the full-scale swing). In addition, an input
gain switch is incorporated with the above definitions.
The UDA1360TS front-end is equipped with a selectable
0 or 6 dB gain, in order to supports 2 V (RMS) input using
a series resistor of 12 kΩ.
For the definition of the pin settings for 1 or 2 V (RMS)
mode given in Table 1, it is assumed that this resistor is
present as a default component.
If the 2 V (RMS) signal input is not needed, the external
resistor should not be used.
2000 Feb 08
4
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
Table 1
Application modes using input gain stage
INPUT GAIN
SWITCH
0 dB
6 dB
0 dB
6 dB
MAXIMUM INPUT
VOLTAGE
2 V (RMS)
1 V (RMS)
1 V (RMS)
0.5 V (RMS)
Mute
UDA1360TS
RESISTOR
(12 kΩ)
Present
Present
Absent
Absent
On recovery from power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:
12288
t
=
---------------
=
279 ms ; where f
s
= 44.1 kHz.
-
f
s
Power-down mode
The PWON pin can control the power saving together with
the optional gain switch for 2 V (RMS) or 1 V (RMS) input.
When the PWON pin is set LOW, the ADC is set to
power-down. When PWON is set to HIGH or to half the
power supply, then either 6 dB gain or 0 dB gain in the
analog front-end is selected.
Application modes
The UDA1360TS can be set to different modes using two
3-level pins and one 2-level pin. The selection of modes is
given in Table 3.
Table 3
PIN
SFOR
PWON
FSEL
Mode selection summary
V
SS
I
2
S-bus
256f
s
1
⁄
V
2 DD
Multiple format output interface
The UDA1360TS supports the following data output
formats;
•
I
2
S-bus with data word length of up to 20 bits
•
MSB-justified serial format with data word length of up to
20 bits.
The output format can be set by the static SFOR pin. When
SFOR is LOW, the I
2
S-bus is selected, when SFOR is set
HIGH the MSB-justified format is selected.
The data formats are illustrated in Fig.4. Left and right data
channel words are time multiplexed.
Decimation filter
The decimation from 128f
s
is performed in two stages.
The first stage realizes 3rd-order sin x/x characteristic.
This filter decreases the sample rate by 16. The second
stage (an FIR filter) consists of 3 half-band filters, each
decimating by a factor of 2.
Table 2
DC cancellation filter characteristics
ITEM
Pass-band ripple
Pass-band gain
Stop band
Droop
Attenuation at DC
Dynamic range
>0.55f
s
at 0.00045f
s
at 0.00000036f
s
0 to 0.45f
s
CONDITION
VALUE
(dB)
none
0
−60
0.031
>40
>110
V
DD
MSB
6 dB gain
384f
s
test mode
−
power-down 0 dB gain
2000 Feb 08
5
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