UDA1431T
16-bit, 48 kHz, low-cost stereo current DAC
Rev. 04 — 30 May 2006
Product data sheet
1. General description
The UDA1431T is a 16-bit, 48 kHz, single-chip stereo DAC employing bitstream
conversion techniques.
The UDA1431T supports the I
2
S-bus data format with word lengths of up to 24 bits,
MSB justified and can be operated with a 256f
s
master clock mode.
The audio outputs meet the IEC 61938 specification.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
Low power consumption
Analog power supply voltage from 10.8 V to 13.2 V
Digital power supply voltage from 3.1 V to 3.5 V
Master clock frequencies of 256f
s
Supports sampling frequencies up to 48 kHz
Integrated digital filter
No analog post filtering required for DAC
Slave mode only applications
I
2
S-bus input interface: 16-bit, 18-bit, 20-bit and 24-bit format compatible
CMOS levels compatible digital inputs and outputs
Very easy application
Advanced audio configuration:
N
Stereo line output
N
High linearity, wide dynamic range and low distortion
I
Small package size (SO14)
3. Applications
I
I
I
I
PC audio applications
Car radio applications
DVD players
Digital set-top boxes
Philips Semiconductors
UDA1431T
16-bit, 48 kHz, low-cost stereo current DAC
4. Quick reference data
Table 1.
Quick reference data
V
DDA
= 12.0 V; V
DDD
= 3.3 V; T
amb
= 25
°
C; f
s
= 48 kHz; f
i
= 1 kHz; all voltages referenced to ground
(pins V
SSA
and V
SSD
); unless otherwise specified.
Symbol
Supplies
V
DDA
V
DDD
I
DDA
analog supply voltage
(for DAC)
digital supply voltage
analog supply current
(for DAC)
V
DDA
= 12.0 V
operating
power-down
I
DDD
digital supply current
V
DDD
= 3.3 V
operating
power-down
P
tot
T
amb
V
o(rms)
(THD + N)/S
total power dissipation
ambient temperature
output voltage
(RMS value)
total harmonic
distortion-plus-noise to
signal ratio
signal-to-noise ratio
channel separation
at 0 dB; from
1 kHz to 20 kHz
at 0 dB
at
−60
dB
[2][3]
[2][4]
[3][5]
[1]
[1]
Parameter
Conditions
Min
10.8
3.1
-
-
-
-
[1]
Typ
12.0
3.3
6.6
0.8
7.0
6.8
102
-
1.880
−66
−32.5
94
98
Max
13.2
3.5
-
-
-
-
-
65
1.925
-
-
-
-
Unit
V
V
mA
mA
mA
mA
mW
°C
V
dB
dB
dB
dB
operating
-
5
1.575
−62
-
89
85
Digital-to-analog converter
S/N
α
cs
[1]
[2]
[3]
[4]
[5]
A 1 kHz at 0 dB sine wave input is applied.
(THD + N)/S is the power ratio between the sum of noise and distortion and the output signal.
Measurement is performed with a 22 kHz low-pass filter and is unweighted.
Measurement is performed with a ITU-R-2K filter and is unweighted.
S/N is the power ratio between the output signal and the noise measured with no signal applied.
5. Ordering information
Table 2.
Type
number
UDA1431T
Ordering information
Package
Name
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
Version
SOT108-1
UDA1431T_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 30 May 2006
2 of 17
Philips Semiconductors
UDA1431T
16-bit, 48 kHz, low-cost stereo current DAC
6. Block diagram
V
DDD
DVREF AVREF
11
8
V
DDA
9
PD_N
12
UDA1431T
13
4
2
3
I
2
S-BUS
INTERFACE
14
MCLK
BCLK
WS
SDI
UPSAMPLING
FILTERING
NOISE SHAPING
CURRENT
DAC
AMPLIFIER
6
ROUT
UPSAMPLING
FILTERING
NOISE SHAPING
DIGITAL
1
V
SSD
CURRENT
DAC
ANALOG
7
V
SSA
AMPLIFIER
10
LOUT
001aac962
Fig 1. Block diagram
7. Pinning information
7.1 Pinning
V
SSD
WS
SDI
BCLK
i.c.
ROUT
V
SSA
1
2
3
4
5
6
7
001aac963
14 V
DDD
13 MCLK
12 PD_N
UDA1431T
11 DVREF
10 LOUT
9
8
V
DDA
AVREF
Fig 2. Pin configuration
7.2 Pin description
Table 3.
Symbol
V
SSD
WS
SDI
BCLK
i.c.
Pin description
Pin
1
2
3
4
5
Description
digital ground
word select input
serial audio data input
bit clock input
internally connected; do not connect or connect to V
DDD
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UDA1431T_4
Product data sheet
Rev. 04 — 30 May 2006
3 of 17
Philips Semiconductors
UDA1431T
16-bit, 48 kHz, low-cost stereo current DAC
Pin description
…continued
Pin
6
7
8
9
10
11
12
13
14
Description
right channel output
analog ground (for DAC)
regulator decoupling
analog supply voltage (for DAC)
left channel output
internal reference voltage (digital part)
power-down input (active LOW)
master clock input (256f
s
)
digital supply voltage
Table 3.
Symbol
ROUT
V
SSA
AVREF
V
DDA
LOUT
DVREF
PD_N
MCLK
V
DDD
8. Functional description
8.1 Master clock
The UDA1431T operates in slave mode only. Therefore, in all applications the system
devices must provide a master clock (pin MCLK) at 256f
s
for correct operation. The master
clock must be locked in frequency to the digital interface input signals.
The UDA1431T supports sampling frequencies up to 48 kHz.
8.2 Data formats
The I
2
S-bus formats are shown in
Figure 3.
Left and right data channel words are time multiplexed.
The UDA1431T supports I
2
S-bus formats with data word length up to 24 bits.
The BCLK clock can be up to 48f
s
, or in other words the BCLK frequency is 48 times or
less the word select frequency (pin WS): f
BCLK
≤
48
×
f
WS
.
Important:
The WS edge MUST fall on the negative edge of the BCLK at all times for
proper operation of the digital interface.
8.3 Noise shaper
The 1st-order noise shaper operates at 32f
s
. It shifts in-band quantization noise to
frequencies well above the audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog
signal using a current DAC.
8.4 Reset
After turning on the power supplies of the device, the device must be reset. This is done
by applying a logic 0 pulse on PD_N (pin 12) during at least 8 full MCLK periods. If PD_N
(pin 12) has a value of logic 0 at start-up, it must be set to logic 1 only after 8 full MCLK
periods. The device is ready to receive audio data only after 128 MCLK periods from the
end of the reset.
UDA1431T_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 30 May 2006
4 of 17
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Product data sheet
Rev. 04 — 30 May 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UDA1431T_4
Philips Semiconductors
WS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
MSB
R
B2
R
B3
R
B14
R
B15
R
LSB
R
MSB
L
SDI
MSB
L
B2
L
B3
L
B14
L
B15
L
LSB
L
I
2
S-BUS FORMAT
WS
LEFT CHANNEL
RIGHT CHANNEL
16-bit, 48 kHz, low-cost stereo current DAC
BCLK
SDI
LSB
R
MSB
L
B2
L
B3
L
B14
L
B15
L
LSB
L
MSB
R
B2
R
B3
R
B14
R
B15
R
LSB
R
MSB
L
001aac967
I
2
S-BUS FORMAT IN 16-BIT MODE
UDA1431T
5 of 17
Fig 3. I
2
S-bus data formats
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