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MT8VDDT1664HG-265

Description
DDR DRAM Module, 16MX64, 0.75ns, CMOS, PDMA200,
Categorystorage    storage   
File Size683KB,37 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT8VDDT1664HG-265 Overview

DDR DRAM Module, 16MX64, 0.75ns, CMOS, PDMA200,

MT8VDDT1664HG-265 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid102871545
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time0.75 ns
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeR-PDMA-N200
memory density1073741824 bit
Memory IC TypeDDR DRAM MODULE
memory width64
Number of terminals200
word count16777216 words
character code16000000
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX64
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeDIMM
Encapsulate equivalent codeDIMM200,24
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
power supply2.5 V
Certification statusNot Qualified
refresh cycle4096
Maximum standby current0.024 A
Maximum slew rate2.6 mA
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch0.6 mm
Terminal locationDUAL
128MB, 256MB, 512MB: (x64, SR) 200-Pin DDR SODIMM
Features
DDR SDRAM Small-Outline DIMM
MT8VDDT1664H – 128MB
MT8VDDT3264H – 256MB
MT8VDDT6464H – 512MB
For the latest data sheet, refer to the Micron’s Web site:
www.micron.com/products/modules
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 128MB (16 Meg x 64), 256MB (32 Meg x 64), or
512MB (64 Meg x 64)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
• 15.625µs (128MB), 7.8125µs (256MB, 512MB)
maximum average periodic refresh interval
• Gold edge contacts
Figure 1:
200-Pin SODIMM (MO-224)
Height 1.25in. (31.75mm)
Options
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
1
• Memory Clock, Speed, CAS Latency
2
6ns (166 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• Operating Temperature
Commercial (0°C
T
A
+70°C)
Industrial (-40°C
T
A
+85°C)
• PCB Height
1.25in. (31.75mm)
Marking
G
Y
-335
-262
1
-26A
1
-265
none
IT
Notes: 1. Contact Micron for product availability.
2. CL = CAS (READ) latency.
pdf: 09005aef8092973f, source: 09005aef80921669
DD8C16_32_64x64H_1.fm - Rev. B 7/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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