a
FEATURES
Improved Replacement for Burr-Brown
OPA-111 and OPA-121 Op Amp
LOW NOISE
2 V p-p max, 0.1 Hz to 10 Hz
10 nV/√Hz max at 10 kHz
11 fA p-p Current Noise 0.1 Hz to 10 Hz
Low Noise, Low Drift
FET Op Amp
AD645
CONNECTION DIAGRAMS
TO-99 (H) Package
8-Pin Plastic Mini-DIP
(N) Package
CASE
OFFSET
NULL
–IN
+IN
–VS
OFFSET
NULL
8
1
7
HIGH DC ACCURACY
250 V max Offset Voltage
1 V/ C max Drift
1.5 pA max Input Bias Current
114 dB Open-Loop Gain
Available in Plastic Mini-DIP, 8-Pin Header Packages, or
Chip Form
APPLICATIONS
Low Noise Photodiode Preamps
CT Scanners
Precision I-V Converters
V
O T
PR RIF
IM D
ED
1
2
3
4
TOP VIEW
8 NC
+V
AD645
7 +VS
– IN
6 OUTPUT
5 OFFSET
NULL
3
+ IN
2
6
OUTPUT
AD645
4
–V
5
OFFSET
NULL
NC = NO CONNECT
NOTE: CASE IS CONNECTED
TO PIN 8
PRODUCT DESCRIPTION
The AD645 is available in six performance grades. The AD645J
and AD645K are rated over the commercial temperature range
of 0°C to +70°C. The AD645A, AD645B, and the ultra-
precision AD645C are rated over the industrial temperature
range of –40°C to +85°C. The AD645S is rated over the military
temperature range of –55°C to +125°C and is available
processed to MIL-STD-883B.
The AD645 is available in an 8-pin plastic mini-DIP, 8-pin
header, or in die form.
PRODUCT HIGHLIGHTS
The AD645 is a low noise, precision FET input op amp. It of-
fers the pico amp level input currents of a FET input device
coupled with offset drift and input voltage noise comparable to a
high performance bipolar input amplifier.
The AD645 has been improved to offer the lowest offset drift in
a FET op amp, 1
µV/°C.
Offset voltage drift is measured and
trimmed at wafer level for the lowest cost possible. An inher-
ently low noise architecture and advanced manufacturing tech-
niques result in a device with a guaranteed low input voltage
noise of 2
µV
p-p, 0.1 Hz to 10 Hz. This level of dc performance
along with low input currents make the AD645 an excellent
choice for high impedance applications where stability is of
prime concern.
1k
VOLTAGE NOISE SPECTRAL DENSITY
nV/ Hz
1. Guaranteed and tested low frequency noise of 2
µV
p-p max
and 20 nV/√Hz at 100 Hz makes the AD645C ideal for low
noise applications where a FET input op amp is needed.
2. Low V
OS
drift of 1
µV/°C
max makes the AD645C an excel-
lent choice for applications requiring ultimate stability.
3. Low input bias current and current noise (11 fA p-p 0.1 Hz to
10 Hz) allow the AD645 to be used as a high precision
preamp for current output sensors such as photodiodes, or as
a buffer for high source impedance voltage output sensors.
30
25
NUMBER OF UNITS
100
20
15
10
10
5
1.0
1
10
100
FREQUENCY – Hz
1k
10k
0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
INPUT OFFSET VOLTAGE DRIFT–
µV/
°
C
Figure 1. AD645 Voltage Noise Spectral Density vs.
Frequency
Figure 2. Typical Distribution of Average Input Offset
Voltage Drift (196 Units)
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD645–SPECIFICATIONS
(@ +25 C, and
Model
Conditions
1
INPUT OFFSET VOLTAGE
1
Initial Offset
Offset
Drift (Average)
vs. Supply (PSRR)
vs. Supply
INPUT BIAS CURRENT
2
Either Input
Either Input
@ T
MAX
Either Input
Offset Current
Offset Current
@ T
MAX
INPUT VOLTAGE NOISE
Min
T
MIN
–T
MAX
90
T
MIN
–T
MAX
V
CM
= 0 V
V
CM
= 0 V
V
CM
= +10 V
V
CM
= 0 V
V
CM
= 0 V
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 0.1 to 10 Hz
f = 0.1 thru 20 kHz
100
300
3
110
100
0.7/1.8
16/115
0.8/1.9
0.1
2/6
1.0
20
10
9
8
11
0.6
2
V
O
= 20 V p-p
R
LOAD
= 2 kΩ
V
OUT
= 20 V p-p
R
LOAD
= 2 kΩ
16
1
32
2
6
8
5
3.0
50
30
15
10
20
1.1
15 V dc, unless otherwise noted)
Min
AD645K/B
Typ Max
Min
AD645C
Typ Max
Min
AD645S
Typ Max
Units
µV
µV
µV/°C
dB
dB
pA
pA
pA
pA
pA
3.3
50
30
15
10
20
1.1
µV
p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA p-p
fA/√Hz
MHz
kHz
V/µs
µs
µs
µs
AD645J/A
Typ
Max
500
1000
10/5
94
90
3/5
50
100
1
110
100
250
400
5/2
94
90
50
75
0.5
110
100
1.8
115
1.9
0.1
6
250
300
1
90
86
3
100
500
4
110
95
1.8
1800
1.9
0.1
100
500
1500
10
0.7/1.8 1.5/3
16/115
0.8/1.9
0.1
0.5
2/6
1.0
20
10
9
8
11
0.6
2
16
1
32
2
6
8
5
16
1
2.5
40
20
12
10
15
0.8
5
1.0
0.5
1.0
1
20
10
9
8
11
0.6
2
32
2
6
8
5
2
40
20
12
10
15
0.8
1.0
20
10
9
8
11
0.6
2
16
1
32
2
6
8
5
INPUT CURRENT NOISE
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
SETTLING TIME
3
To 0.1%
To 0.01%
Overload Recovery
4
Total Harmonic
Distortion
INPUT IMPEDANCE
Differential
Common-Mode
INPUT VOLTAGE RANGE
Differential
5
Common-Mode Voltage
Over Max Oper. Range
Common-Mode
Rejection Ratio
OPEN-LOOP GAIN
50% Overdrive
f = 1 kHz
R
LOAD
≥
2 kΩ
V
O
= 3 V rms
V
DIFF
=
±
1 V
0.0006
10
12
1
10
14
2.2
±
20
+11, –10.4
0.0006
10
12
1
10
14
2.2
±
20
+11, –10.4
0.0006
10
12
1
10
14
2.2
±
20
+11, –10.4
0.0006
10
12
1
10
14
2.2
±
20
+11, –10.4
%
Ω
pF
Ω
pF
V
V
V
dB
dB
dB
dB
V
V
mA
mA
V
V
mA
±
10
±
10
V
CM
=
±
10 V
T
MIN
–T
MAX
V
O
=
±
10 V
R
LOAD
≥
2 kΩ
T
MIN
–T
MAX
90
±
10
±
10
94
90
120
114
±
10
±
10
±
5
±
10
±
10
94
90
120
114
±
10
±
10
±
5
±
10
±
10
90
86
114
110
±
10
±
10
±
5
110
100
130
110
100
130
110
100
130
110
100
130
114
OUTPUT CHARACTERISTICS
Voltage
R
LOAD
≥
2 kΩ
T
MIN
–T
MAX
Current
V
OUT
=
±
10 V
Short Circuit
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Transistor Count
±
10
±
10
±
5
±
11
±
10
±
15
±
15
3.0
62
±
11
±
10
±
15
±
15
3.0
62
±
11
±
10
±
15
±
15
3.0
62
±
11
±
10
±
15
±
15
3.0
62
±
5
# of Transistors
±
18
3.5
±
5
±
18
3.5
±
5
±
18
3.5
±
5
±
18
3.5
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at T
A
= +25°C.
2
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T
A
= +25°C. For higher temperature, the current doubles every 10°C.
3
Gain = –1, R
LOAD
= 2 kΩ.
4
Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input.
5
Defined as the maximum continuous voltage between the inputs such that neither input exceeds
±
10 V from ground.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. B
AD645
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Internal Power Dissipation
2
(@ T
A
= +25°C)
8-Pin Header Package . . . . . . . . . . . . . . . . . . . . . . 500 mW
8-Pin Mini-DIP Package . . . . . . . . . . . . . . . . . . . . 750 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
V
S
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +V
S
and –V
S
Storage Temperature Range (H) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD645J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD645A/B/C . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD645S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range
(Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
Thermal Characteristics:
8-Pin Plastic Mini-DIP Package:
θ
JA
= 100°C/Watt
8-Pin Header Package:
θ
JA
= 200°C/Watt
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD645 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
WARNING!
ESD SENSITIVE DEVICE
METALIZATION PHOTOGRAPH
Model
1
AD645JN
AD645KN
AD645AH
AD645BH
AD645CH
AD645SH/883B
Temperature Range
0°C to +70°C
0°C to +70°C
– 40°C to +85°C
– 40°C to +85°C
– 40°C to +85°C
– 55°C to +125°C
Package Option
2
N-8
N-8
H-08A
H-08A
H-08A
H-08A
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
NOTES
1
Chips are also available.
2
N = Plastic Mini-DIP; H = Metal Can.
+V
S
2
7
AD645
3
4
1
10k
6
5
V
OS
ADJUST
–V
S
Figure 3. AD645 Offset Null Configuration
800
700
100
20
120
110
25
NUMBER OF UNITS
NUMBER OF UNITS
80
70
60
50
40
30
20
500
400
300
200
100
NUMBER OF UNITS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
600
90
15
10
5
10
0
–1.0 –0.8 –0.6 –0.4 –0.2 0.0
0
0.2
0.4
0.6
0.8
1.0
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
INPUT OFFSET VOLTAGE – mV
INPUT BIAS CURRENT – pA
INPUT VOLTAGE NOISE –
µV
p-p
Figure 4. Typical Distribution of Input
Offset Voltage (1855 Units)
Figure 5. Typical Distribution of Input
Bias Current (576 Units)
Figure 6. Typical Distribution of 0.1 Hz
to 10 Hz Voltage Noise (202 Units)
REV. B
–3–
AD645–Typical Characteristics
(@ +25 C,
100
15 V unless otherwise noted)
1000
Hz
1k
Hz
CURRENT NOISE SPECTRAL DENSITY – fA/
√
Hz
R
S
= 10MΩ
VOLTAGE NOISE SPECTRAL DENSITY – nV/
VOLTAGE NOISE SPECTRAL DENSITY – nV
R
S
= 1MΩ
100
R
S
= 100kΩ
10
100
1.0
10
10
R
S
= 100Ω
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY – Hz
0
1
10
100
1k
10k
100k
FREQUENCY – Hz
1
0.1
1.0
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 7. Current Noise Spectral
Density vs. Frequency
Figure 8. Voltage Noise Spectral
Density vs. Frequency
Figure 9. Voltage Noise Spectral
Density vs. Frequency for Various
Source Resistances
1k
25
fo = 1kHz
100
nV/
√
Hz
100
CURRENT NOISE – fA/
√
Hz
20
10
VOLTAGE NOISE SPECTRAL DENSITY @ 1kHz – nV/
√
Hz
1k
INPUT VOLTAGE NOISE –
µV
p-p
100
–
VOLTAGE NOISE
CURRENT NOISE
15
1
NOISE BANDWIDTH: 0.1 to 10Hz
NOISE OF AD645
AND RESISTOR
10
10
SOURCE
RESISTANCE
RESISTOR NOISE
ONLY
1.0
100
1k
10k
100k
1M
10M
100M
10
VOLTAGE NOISE
0.1
1.0
10
3
10
4
10
5
10
6
10
7
SOURCE RESISTANCE –
Ω
10
8
10
9
5
– 60 – 40
– 20
0
20
40
60
80
0.01
100 120 140
TEMPERATURE – C
SOURCE RESISTANCE –
Ω
Figure 10. Input Voltage Noise vs.
Source Resistance
Figure 11. Voltage and Current
Noise Spectral Density vs.
Temperature
Figure 12. Voltage Noise Spectral
Density @ 1 kHz vs. Source
Resistance
50
CHANGE IN INPUT OFFSET VOLTAGE –
µV
150
10
– 9
10
– 9
25
75
INPUT
BIAS
CURRENT
10
– 11
10
–11
T
A
= 25°C TO T
A
= 85°C
0
0
10
– 12
INPUT
OFFSET
CURRENT
10
– 13
10
–12
– 25
–75
10
– 13
– 50
0
1
2
3
4
5
WARM-UP TIME – Minutes
–150
0
1
2
3
4
5
10
– 14
– 60 – 40
– 20
0
20
40
60
10
– 14
80 100 120 140
TIME FROM THERMAL SHOCK – Minutes
TEMPERATURE – C
Figure 13. Change in Input Offset
Voltage vs. Warmup Time
Figure 14. Change in Input Offset
Voltage vs. Time from Thermal
Shock
Figure 15. Input Bias and Offset
Currents vs. Temperature
–4–
REV. B
INPUT OFFSET CURRENT – Amps
V
S
=
±15V
CHANGE IN INPUT OFFSET VOLTAGE –
µV
T
A
= +25 C
INPUT BIAS CURRENT – Amps
10
– 10
10
– 10
AD645
10
POWER SUPPLY REJECTION – dB
120
120
INPUT BIAS CURRENT – pA
+ PSRR
80
– PSRR
60
COMMON-MODE REJECTION – dB
T
A
= +25°C
V
S
=
±15V
H PACKAGE
100
100
80
1.0
60
40
40
20
20
0.1
–20
0
0
–15 –10
–5
5
10
0
COMMON MODE VOLTAGE – Volts
15
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
1
10
100
10k
100k
1k
FREQUENCY – Hz
1M
10M
Figure 16. Input Bias Current vs.
Common-Mode Voltage
Figure 17. Power Supply Rejection
vs. Frequency
Figure 18. Common-Mode
Rejection vs. Frequency
120
110
– 45
3.0
4.0
100
COMMON-MODE REJECTION – dB
OPEN-LOOP GAIN – dB
80
– 90
GAIN-BANDWIDTH PRODUCT – MHz
PHASE
PHASE SHIFT – Degrees
110
2.0
SLEW RATE
100
60
40
GAIN
–135
90
1.0
GAIN-BANDWIDTH
2.0
20
80
0
– 180
70
– 15
– 20
– 10
–5
0
5
10
15
10
100
COMMON MODE VOLTAGE – Volts
1k
10k
100k
FREQUENCY – Hz
1M
10M
0
– 60 – 40 – 20
0
20
40
60
80
1.0
100 120 140
TEMPERATURE – C
Figure 19. Common-Mode
Rejection vs. Input Common-Mode
Voltage
4.0
Figure 20. Open-Loop Gain and
Phase Shift vs. Frequency
Figure 21. Gain-Bandwidth Product
and Slew Rate vs. Temperature
160
V
S
=
±15V
V
O
=
±10V
RL = 2kΩ
35
GAIN-BANDWIDTH PRODUCT – MHz
4.0
150
OPEN-LOOP GAIN – dB
30
OUTPUT VOLTAGE – Volts p-p
SLEW RATE – Volts/µs
3.0
140
25
20
SLEW RATE
3.0
130
15
2.0
GAIN-BANDWIDTH
2.0
120
10
110
5
1.0
0
5
10
15
20
SUPPLY VOLTAGE – ±Volts
100
– 60 – 40 – 20
0
20 40
60 80
TEMPERATURE – C
100 120 140
0
1k
10k
100k
FREQUENCY – Hz
1M
Figure 22. Gain-Bandwidth and
Slew Rate vs. Supply Voltage
Figure 23. Open-Loop Gain vs.
Temperature
Figure 24. Large Signal Frequency
Response
REV. B
–5–
SLEW RATE – Volts/µs
3.0
51mcu
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