W256
12 Output Buffer for 2 DDR and 3 SRAM DIMMS
Features
• One input to 12 output buffer/drivers
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266 MHz and 333 MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 28-pin SSOP package
Functional Description
The W256 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 12 outputs.
Designers can configure these outputs to support 3 unbuffered
standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can
be used in conjunction with the W250-02 or similar clock
synthesizer for the VIA Pro 266 chipset.
The W256 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull-up).
Block Diagram
VDD3.5_2.5
BUF_IN
DDR0T_SDRAM0
DDR0C_SDRAM1
DDR1T_SDRAM2
SDATA
SCLOCK
PWR_DWN#
Pin Configuration
[1]
FBOUT
SSOP
Top View
FBOUT
*PWR_DWN#
DDR0T_SDRAM0
DDR0C_SDRAM1
VDD3.3_2.5
GND
DDR1T_SDRAM2
DDR1C_SDRAM3
VDD3.3_2.5
BUF_IN
GND
DDR2T_SDRAM4
DDR2C_SDRAM5
VDD3.3_2.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SEL_DDR*
DDR5T_SDRAM10
DDR5C_SDRAM11
VDD3.3_2.5
GND
DDR4T_SDRAM8
DDR4C_SDRAM9
VDD3.3_2.5
GND
DDR3T_SDRAM6
DDR3C_SDRAM7
GND
SCLK
SDATA
SMBus
Decoding
&
Powerdown
Control
DDR1C_SDRAM3
DDR2T_SDRAM4
DDR2C_SDRAM5
DDR3T_SDRAM6
DDR3C_SDRAM7
DDR4T_SDRAM8
DDR4C_SDRAM9
DDR5T_SDRAM10
DDR5C_SDRAM11
SEL_DDR
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Cypress Semiconductor Corporation
Document #: 38-07256 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 30, 2004
W256
Pin Summary
Name
SEL_DDR
28
Pins
Description
Input to configure for DDR-ONLY mode or STANDARD SDRAM mode.
1 = DDR-ONLY mode.
0 = STANDARD SDRAM mode.
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, all the buffers
will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM output, all
the buffers will be configured as STANDARD SDRAM outputs.
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM mode.
SMBus clock input.
SMBus data input.
Reference input from chipset.
2.5V input for DDR-ONLY mode; 3.3V input for
STANDARD SDRAM mode.
Feedback clock for chipset.
Output voltage depends on VDD3.3_2.5V.
Active LOW input to enable Power Down mode; all outputs will be pulled LOW.
Clock outputs.
These outputs provide copies of BUF_IN. Voltage swing depends
on VDD3.3_2.5 power supply.
Clock outputs.
These outputs provide complementary copies of BUF_IN when
SEL_DDR is active. These outputs provide copies of BUF_IN when SEL_DDR is
inactive. Voltage swing depends on VDD3.3_2.5 power supply.
Connect to 2.5V power supply when W256 is configured for DDR-ONLY mode.
Connect to 3.3V power supply, when W256 is configured for standard SDRAM
mode.
Ground.
SCLK
SDATA
BUF_IN
FBOUT
PWR_DWN#
DDR[0:5]T_SDRAM
[0,2,4,6,8,10]
16
15
10
1
2
3, 7, 12, 19, 23, 27
DDR[0:5]C_SDRAM 4, 8, 13, 18, 22, 26
[1,3,5,7,9, 11]
VDD3.3_2.5
5, 9, 14, 21, 25
GND
6, 11, 17, 20, 24
Document #: 38-07256 Rev. *C
Page 2 of 9
W256
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 — Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 — Bits 7, 6, 5, 4, 3, 2, 1, 0
.–
.
Byte N — Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the W256 is:
Table 1.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
––
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
–
19, 18
12, 13
–
–
7, 8
–
3, 4
Description
Reserved, drive to 0
DDR3T_SDRAM6,
DDR3C_SDRAM7
DDR2T_SDRAM4,
DDR2C_SDRAM5
Reserved, drive to 0
Reserved, drive to 0
DDR1T_SDRAM2,
DDR1C_SDRAM3
Reserved, drive to 0
DDR0T_SDRAM0,
DDR0C_SDRAM1
Default
1
1
1
1
1
1
1
1
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Pin #
–
–
–
1
Description
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
FBOUT
Default
0
0
0
1
1
1
1
1
Bit 3 27, 26 DDR5T_SDRAM10,
DDR5C_SDRAM11
Bit 2
–
Reserved, drive to 0
Bit 1 23, 22 DDR4T_SDRAM8,
DDR4C_SDRAM9
Bit 0
–
Reserved, drive to 0
Document #: 38-07256 Rev. *C
Page 3 of 9
W256
Maximum Ratings
Supply Voltage to Ground Potential ..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN) ............ –0.5V to V
DD
+0.5
Storage Temperature .................................. –65°C to +150°C
Static Discharge Voltage ............................................>2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
[2]
Parameter
V
DD3.3
V
DD2.5
T
A
C
OUT
C
IN
Supply Voltage
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
Description
Min.
3.135
2.375
0
6
5
Typ.
Max.
3.465
2.625
70
Unit
V
V
°C
pF
pF
Electrical Characteristics
Over the Operating Range
Parameter
V
IL
V
IH
I
IL
I
IH
I
OH
I
OL
V
OL
V
OH
I
DD
I
DD
I
DDS
V
OUT
V
OC
IN
DC
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output HIGH Current
Output LOW Current
Output LOW Voltage
[3]
Output HIGH Voltage
[3]
Supply Current
[3]
(DDR-Only mode)
Supply Current
(DDR-Only mode)
Supply Current
Output Voltage Swing
Output Crossing Voltage
Input Clock Duty Cycle
V
IN
= 0V
V
IN
= V
DD
V
DD
= 2.375V
V
OUT
= 1V
V
DD
= 2.375V
V
OUT
= 1.2V
I
OL
= 12 mA, V
DD
= 2.375V
I
OH
= –12 mA, V
DD
= 2.375V
Unloaded outputs, 133 MHz
Loaded outputs, 133 MHz
PWR_DWN# = 0
See Test Circuity (Refer to
Figure 1)
0.7
(V
DD
/2)
–0.1
48
V
DD
/2
1.7
400
500
100
V
DD
+ 0.6
(V
DD
/2)
+0.1
52
–18
26
–32
35
0.6
Test Conditions
For all pins except SMBus
2.0
50
50
Min.
Typ.
Max.
0.8
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
µA
V
V
%
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07256 Rev. *C
Page 4 of 9
W256
Switching Characteristics
[4]
Parameter
–
–
t
3
t
4
t
3d
t
4d
t
5
t
6
t
7
t
8
Duty
Name
Operating Frequency
Cycle
[4,5]
= t
2
÷
t
1
Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs.
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
Measured between 20% to 80% of
output (Refer to
Figure 1)
Measured between 20% to 80% of
output (Refer to
Figure 1)
All outputs equally loaded
All outputs equally loaded
5
5
Test Conditions
Min.
66
IN
DC
–5%
1.0
1.0
0.5
0.5
Typ.
Max.
180
IN
DC
+5%
2.50
2.50
1.50
1.50
100
150
10
10
Unit
MHz
%
V/ns
V/ns
V/ns
V/ns
ps
ps
ns
ns
SDRAM Rising Edge Rate
[4]
SDRAM Falling Edge Rate
[4]
DDR Rising Edge Rate
[4]
DDR Falling Edge Rate
[4]
Output to Output Skew
[4]
Output t4o Output Skew for
SDRAM
[2]
SDRAM Buffer LLProp.
Delay
[4]
SDRAM Buffer HH Prop. Delay
[4]
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Switching Waveforms
Duty Cycle Timing
t
1
t
2
All Outputs Rise/Fall Time
2.4V
0.4V
t
3
2.4V
0.4V
t
4
3.3V
0V
OUTPUT
Output-Output Skew
OUTPUT
OUTPUT
t
5
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Document #: 38-07256 Rev. *C
Page 5 of 9
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