Freescale Semiconductor
Data Sheet
Document Number: MCF5213EC
Rev. 3, 05/2007
MCF5213
MCF5213 ColdFire
Microcontroller
Supports MCF5213,
MCF5212, & MCF5211
The MCF5213 is a member of the ColdFire
®
family of
reduced instruction set computing (RISC) microprocessors.
This document provides an overview of the 32-bit MCF5213
microcontroller, focusing on its highly integrated and diverse
feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to
256 Kbytes of flash memory and 32 Kbytes of static random
access memory (SRAM). On-chip modules include:
• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with Multiply
Accumulate (MAC) Unit and hardware divider
• FlexCAN controller area network (CAN) module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Inter-integrated circuit (I2C™) bus controller
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter
(ADC)
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM), and pulse accumulation
• Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer
• Two 16-bit periodic interrupt timers (PITs)
• Programmable software watchdog timer
• Interrupt controller capable of handling 57 sources
• Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)
• Test access/debug port (JTAG, BDM)
LQFP–64
10 mm x 10 mm
QFN–64
9 mm x 9 mm
MAPBGA–81
10 mm x 10 mm
LQFP–100
14 mm x 14 mm
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Table of Contents
1
MCF5213 Family Configurations . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .21
1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .21
1.8 I
2
C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.9 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.10 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.11 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.12 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .23
1.13 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .23
1.14 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .23
1.15 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .24
1.16 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .30
2.5 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .31
2.7 Clock Source Electrical Specifications . . . . . . . . . . . . .32
2.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .33
2.9 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.10 I
2
C Input/Output Timing Specifications . . . . . . . . . . . . .35
2.11 Analog-to-Digital Converter (ADC) Parameters . . . . . .36
2.12 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . . .37
2.13 DMA Timers Timing Specifications . . . . . . . . . . . . . . . .38
2.14 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .38
2.15 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . .39
2.16 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .41
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .43
3.1 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .43
3.2 64 QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3 81 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . .50
3.4 100-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .52
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 8. Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . .
Figure 9. QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . .
Figure 11.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . .
Figure 12.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . .
Figure 13.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . .
Figure 15.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . .
37
38
39
40
40
40
41
42
List of Tables
Table 1. MCF5213 Family Configurations . . . . . . . . . . . . . . . . . . 3
Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 12
Table 3. Pin Functions by Primary and Alternate Purpose . . . . 16
Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Mode Selection Signals . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Queued Serial Peripheral Interface (QSPI) Signals. . . 21
Table 10.I
2
C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15.PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 24
Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19.Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 26
Table 20.Current Consumption in Low-Power Mode
,
. . . . . . . . . 27
Table 21.Typical Active Current Consumption Specifications. . . 28
Table 22.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 28
Table 23.SGFM Flash Program and Erase Characteristics . . . . 30
Table 24.SGFM Flash Module Life Characteristics . . . . . . . . . . 30
Table 25.ESD Protection Characteristics, . . . . . . . . . . . . . . . . . 31
Table 26.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 31
Table 27.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32
Table 28.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 29.Reset and Configuration Override Timing . . . . . . . . . . 34
Table 30.I
2
C Input Timing Specifications between I2C_SCL
and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 31.I
2
C Output Timing Specifications between I2C_SCL
and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 32.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 33.Timer Module AC Timing Specifications . . . . . . . . . . . 38
Table 34.QSPI Modules AC Timing Specifications. . . . . . . . . . . 38
Table 35.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 39
Table 36.Debug AC Timing Specification . . . . . . . . . . . . . . . . . . 41
Table 37.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2
3
4
List of Figures
Figure 1. MCF5213 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. 100 LQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . 13
Figure 3. 81 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . . 14
Figure 4. 64 LQFP and 64 QFN Pin Assignments . . . . . . . . . . . 15
Figure 5. GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 6. RSTI and Configuration Override Timing . . . . . . . . . . 34
Figure 7. I
2
C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 36
MCF5213 ColdFire Microcontroller, Rev. 3
2
Freescale Semiconductor
MCF5213 Family Configurations
1
MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations
Module
ColdFire Version 2 Core with MAC
(Multiply-Accumulate Unit)
System Clock
Performance (Dhrystone 2.1 MIPS)
Flash / Static RAM (SRAM)
Interrupt Controller (INTC)
Fast Analog-to-Digital Converter (ADC)
FlexCAN 2.0B Module
Four-channel Direct-Memory Access (DMA)
Watchdog Timer Module (WDT)
Programmable Interval Timer Module (PIT)
Four-Channel General-Purpose Timer
32-bit DMA Timers
QSPI
UARTs
I
2
C
PWM
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
2
Package
63
128/16 Kbytes
5211
5212
5213
•
•
66, 80 MHz
up to 76
256/32 Kbytes
•
•
•
See note
1
•
•
—
•
•
•
•
•
2
3
4
•
•
2
3
4
•
•
2
3
4
•
3
•
3
•
3
•
8
•
8
•
8
•
•
•
•
64 LQFP
64 QFN
81 MAPBGA
•
•
•
•
64 LQFP
81 MAPBGA
•
•
•
•
81 MAPBGA
100 LQFP
1
2
FlexCAN is available on the MCF5211 only in the 64 QFN package.
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is
bonded on smaller packages.
Figure 1
shows a top-level block diagram of the MCF5213. Package options for this family are described later in this document.
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
3
MCF5213 Family Configurations
EzPD
EzPQ
EzPCK
EzPort
EzPCS
GPTn
Interrupt
Controller
PADI – Pin Muxing
QSPI_DIN,
QSPI_DOUT
QSPI_CLK,
QSPI_CSn
Arbiter
4 CH DMA
UART
0
UART
1
UART
2
I
2
C
QSPI
UTXDn
URXDn
URTSn
UCTSn
DTINn/DTOUTn
CANRX
CANTX
PWMn
To/From PADI
SWT
DTIM
0
DTIM
1
DTIM
2
DTIM
3
JTAG_EN
MUX
V2 ColdFire CPU
JTAG
TAP
IFP
OEP
MAC
PMM
AN[7:0]
ADC
32 Kbytes
SRAM
(4K×16)×4
V
STBY
256 Kbytes
Flash
(32K×16)×4
PORTS
(GPIO)
CIM
RSTI
RSTO
V
RH
V
RL
FlexCAN
Edge
Port
PLL OCO
CLKGEN
PIT0
PIT1
GPT
PWM
EXTAL
XTAL
CLKOUT
CLKMOD0 CLKMOD1
To/From Interrupt Controller
Figure 1. MCF5213 Block Diagram
1.1
Features
This document contains information on a new product under development. Freescale reserves the right to change or discontinue
this product without notice. Specifications and information herein are subject to change without notice.
1.1.1
Feature Overview
The MCF5213 family includes the following features:
MCF5213 ColdFire Microcontroller, Rev. 3
4
Freescale Semiconductor
MCF5213 Family Configurations
•
•
•
•
•
•
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16
→
32 or 32×32
→
32 operations
— Illegal instruction decode that allows for 68-Kbyte emulation support
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
2-level trigger
On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply
support
— 256 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard data and remote frames (up to 109 bits long)
– Extended data and remote frames (up to 127 bits long)
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as
Rx or Tx, all supporting standard and extended messages
— Unused MB space can be used as general purpose RAM space
— Listen-only mode capability
— Content-related addressing
— No read/write semaphores
— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
5
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