K4S561632J
Industrial
Synchronous DRAM
256Mb J-die SDRAM Specification
54 TSOP-II with Lead-Free & Halogen-Free
(RoHS compliant)
Industrial Temp. -40 to 85°C
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.11 March 2008
K4S561632J
Table of Contents
Industrial
Synchronous DRAM
1.0 FEATURES .................................................................................................................................... 4
2.0 GENERAL DESCRIPTION ............................................................................................................ 4
3.0 Ordering Information ................................................................................................................... 4
4.0 Package Physical Dimension ...................................................................................................... 5
5.0 FUNCTIONAL BLOCK DIAGRAM................................................................................................. 6
6.0 PIN CONFIGURATION................................................................................................................... 7
7.0 Input/Output Function Description ............................................................................................. 7
8.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................... 8
9.0 DC OPERATING CONDITIONS..................................................................................................... 8
10.0 CAPACITANCE............................................................................................................................ 8
11.0 DC CHARACTERISTICS ............................................................................................................. 9
12.0 AC OPERATING TEST CONDITIONS....................................................................................... 10
13.0 OPERATING AC PARAMETER................................................................................................. 10
14.0 AC CHARACTERISTICS ........................................................................................................... 11
15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS................................................................ 11
16.0 IBIS SPECIFICATION ................................................................................................................ 12
17.0 SIMPLIFIED TRUTH TABLE...................................................................................................... 14
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Rev. 1.11 March 2008
K4S561632J
Revision History
Revision
1.0
1.1
1.11
Month
June
October
March
Year
2007
2007
2008
- First release.
Industrial
Synchronous DRAM
History
- Revised IDD current SPEC
- Revised typo of package dimension
- Added the comment of Halogen-free supporting
- Added Package pin out lead width
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Rev. 1.11 March 2008
K4S561632J
4M x 16Bit x 4 Banks SDRAM
1.0 FEATURES
•
•
•
•
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation
L(U)DQM (x16) for masking
Auto & self refresh
64ms refresh period (8K Cycle)
Lead-Free and Halogen-Free Package
RoHS compliant
Support industrial Temp (-40 to 85 ’C)
Industrial
Synchronous DRAM
•
•
•
•
•
•
•
•
2.0 GENERAL DESCRIPTION
The K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system
clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
3.0 Ordering Information
Part No.
K4S561632J-U
*1
I/P60
K4S561632J-UI/P75
Orgainization
16M x 16
Max Freq.
166MHz (CL=3)
133MHz (CL=3)
Interface
LVTTL
Package
54pin TSOP(II)
Lead-Free & Halogen-Free
*1
Note 1 : 256Mb J-die SDR DRAMs support Lead-Free & Halogen-Free package with Lead-Free package code(-U).
Organization
16Mx16
Row Address
A0~A12
Column Address
A0-A8
Row & Column address configuration
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Rev. 1.11 March 2008
K4S561632J
4.0 Package Physical Dimension
Industrial
Synchronous DRAM
(0.80)
(0.50)
#54
#28
Unit : mm
10.16
±
0.10
(1.50)
(0.80)
0.665
±
0.05
0.210
±
0.05
1.00
±
0.10
22.22
±
0.10
(R
0.1
5)
(10°)
1.20 MAX
0.125
- 0.035
+0.075
(0.50)
#1
(1.50)
#27
(10°)
(10°)
11.76
±
0.20
(10.76)
0.05 MIN
0.
15
)
(0.71)
0.80TYP
[0.80
±
0.08]
(R
0.075 MAX
0.
25
)
(R
(R
0.
25
)
Detail A
Detail B
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
0.30
- 0.05
+0.10
Detail B
(0°
∼
8°)
0.35
- 0.05
+0.10
54Pin TSOP(II) Package Dimension
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[
(10°)
[
(4°)
0.10 MAX
Rev. 1.11 March 2008
0.45 ~ 0.75
0.25TYP
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