ispLSI 3192-70LQI datasheet, PDF

Datasheet> All Categories > semiconductor> Other integrated circuit (IC)> ispLSI 3192-70LQI

ispLSI 3192-70LQI: Descriptioncpld - Complex programmable logic device HI density program logic; Categorysemiconductor Other integrated circuit (IC); File Size147KB，15 Pages; ManufacturerAll Sensors

Download Datasheet Parametric Compare View All

ispLSI 3192-70LQI Overview

cpld - Complex programmable logic device HI density program logic

ispLSI 3192-70LQI Parametric

Parameter Name	Attribute value
Maker	All Sensors
Product Category	CPLD - Complex Programmable Logic Device
RoHS	no
Large battery quantity	192
Maximum operating frequency	70 MHz
delay	10 nS
Number of programmable input/output terminals	32
Working power voltage	5 V
Supply current	320 mA (Typ)
Maximum operating temperature	105 C
Minimum operating temperature	- 40 C
Package/box	PQFP-160
Installation style	SMD/SMT
Supply voltage (maximum)	5.5 V
Supply voltage (minimum)	4.5 V

Preview

Download Datasheet

View All

ispLSI 3192

Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.

www.latticesemi.com/sales/discontinueddevicessales.cfm

High Density Programmable Logic

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 192 I/O Pins

— 9000 PLD Gates

— 384 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 100 MHz Maximum Operating Frequency

—

= 10 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— Supports ISP™ or ispJTAG™ Programming

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

0139/3192

Functional Block Diagram

ORP

Boundary

Scan

Global Routing Pool

D Q

ORP

Array

D Q

Twin

GLB

AND Array

D Q

ORP

D Q

Array

D Q

ORP

Description

The ispLSI 3192 is a High Density Programmable Logic

Device containing 384 Registers, 192 Universal I/O pins,

five Dedicated Clock Input Pins, twelve Output Routing

Pools (ORP), and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3192 features 5-Volt in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3192 offers non-volatile reprogrammability of

the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3192 device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...F3.

There are a total of 24 of these Twin GLBs in the ispLSI

3192 device. Each Twin GLB has 24 inputs, a program-

mable AND array and two OR/Exclusive-OR Arrays, and

eight outputs which can be configured to be either com-

binatorial or registered. All Twin GLB inputs come from

the GRP.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

June 2002

3192_08

ORP

D Q

ispLSI 3192-70LQI Related Products

	ispLSI 3192-70LQI
Description	cpld - Complex programmable logic device HI density program logic
Maker	All Sensors
Product Category	CPLD - Complex Programmable Logic Device
RoHS	no
Large battery quantity	192
Maximum operating frequency	70 MHz
delay	10 nS
Number of programmable input/output terminals	32
Working power voltage	5 V
Supply current	320 mA (Typ)
Maximum operating temperature	105 C
Minimum operating temperature	- 40 C
Package/box	PQFP-160
Installation style	SMD/SMT
Supply voltage (maximum)	5.5 V
Supply voltage (minimum)	4.5 V

Recommended Resources

Multi-channel patrol detection control circuit c

Pulse, triangle wave and sawtooth wave signal generator circuit using 566 04

Circuit diagram of low-power low-frequency amplifier using binary numbers to control gain

GRIA06 application circuit diagram

The most practical basic diagram circuit 33 - AC zero-crossing trigger solid state relay circuit

555 voltage monitor circuit

How long does it take to execute one for loop?: I am using mbed LPC1768. For example, how long does it take to perform the following operation for(int i=0;i<1;i++) once?...; NickYoungYoung ARM Technology

Raspberry Pi 2 Model B Review - by freebsder: [url=home.php?mod=spaceuid=551466]@freebsder[/url]Raspberry Pi 2 Model B Review (I) - A Commercial Victory of Universal Sentiment Raspberry Pi 2 Model B Review (Part 2) - The Hard Power of Raspberry P...; okhxyyo DIY/Open Source Hardware

Questions about VHDL process: entity Mux_4 is port(input1,input2,input3,input4:in std_logic; mux_1,mux_2: in std_logic; mux_outut std_logic); end Mux_4; architecture Behavioral of Mux_4 is signal sel : std_logic_vector(1 downto 0)...; eeleader FPGA/CPLD

DS18B20 programming problem (a few sentences I don't understand): Thank you for your answers!I refer to the DS18B20 program of the expert, and it can be used, but there are a few sentences that I don't understand. Please guide me: (Excerpt from the program)const flo...; heyi000 Microcontroller MCU

2650 Visible light LED communication: I just came into contact with this board. I have been learning it before. I made a photoelectric heart rate transmitter for mobile phones. Now I want to do visible light communication. I use RS encodi...; zynone RF/Wirelessly

Regarding the problem of DSP initialization, please help: [i=s] This post was last edited by dontium on 2015-1-23 13:26[/i] -------------------------- ---- LED.pjt - Debug -------------------------------[Delay.c] \"c:\\ ti\\c5500\\cgtools\\bin\\cl55\" -g -q ...; cewei30mkk Analogue and Mixed Signal

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components