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8032 Pin and Instruction Compatible
Four 8-bit I/O Ports
Three 16-bit Timer/Counters
256 bytes RAM
Full-duplex UART
Asynchronous Port Reset
6 Sources, 2 Level Interrupt Structure
64 Kbytes Program Memory Space
64 Kbytes Data Memory Space
Power Control Modes
Idle Mode
Power-down Mode
On-chip Oscillator
Operating Frequency: 30 MHz
Power Supply: 4.5V to 5.5V
Temperature Range: Military (-55
o
C to 125
o
C)
Packages: Side Brazed 40-pin, MQFPJ 44-pin
QML Q and V with SMD 5962-00518
SCC C an B with Specification SCC9521002
Rad. Tolerant
8-bit ROMless
Microcontroller
80C32E
Description
The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit
microcontroller.
The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6-
source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters.
The fully static design of the 80C32E reduces system power consumption by bringing
the clock frequency down to any value, even DC, without loss of data.
The 80C32E has 2 software-selectable modes of reduced activity for further reduction
in power consumption. In the idle mode the CPU is frozen while the timers, the serial
port and the interrupt system are still operating. In the power-down mode the RAM is
saved and all other functions are inoperative.
Rev. 4149M–AERO–06/03
1
Block Diagram
RxD
TxD
P1
P2
T2
T2EX
P0
P3
XTAL1
XTAL2
ALE
PSEN
CPU
EA
RD
WR
INT
Ctrl
Timer 0
Timer 1
Timer 2
UART
RAM
256x8
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 2 Port 3
C51
CORE
IB-bus
RST
T0
INT0
Pin Configuration
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.1/A1
P0.2/A2
P0.3/A3
P0.4/A4
P0.5/A5
P0.6/A6
P0.7/A7
EA/VPP
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
P0.2/AD2
P0.3/AD3
39
38
37
36
35
34
33
32
31
30
29
P0.0/AD0
P0.1/AD1
P0.0/A0
VCC
NIC*
P1.4
P1.3
P1.2
P1.1
P1.0
INT1
T1
6 5 4 3 2 1 44 43 42 41 40
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
SB40
MQFPJ44
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
P2.2/A10
P2.3/A11
P2.4/A12
P3.7/RD
NIC*
P2.0/A8
P2.1/A9
XTAL2
XTAL1
VSS
Note:
NIC: No Internal Connection
2
80C32E
4149M–AERO–06/03
80C32E
Pin Description
Mnemonic
V
SS
V
CC
Type
I
I
Name and Function
Ground:
0V reference
Power Supply:
This is the power supply voltage for normal, idle and
power-down operation
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 pins must be polarized to Vcc or Vss in order to prevent any
parasitic current consumption. Port 0 is also the multiplexed low-order
address and data bus during access to external program and data
memory. In this application, it uses strong internal pull-up when emitting
1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current because of the internal pull-ups.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
RXD (P3.0):
Serial input port
TXD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
INT1 (P3.3):
External interrupt 1
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to V
SS
permits a
power-on reset using only an external capacitor to V
CC.
P0.0-P0.7
I/O
P1.0-P1.7
I/O
P2.0-P2.7
I/O
I/O
I
O
P3.0-P3.7
I
I
I
I
O
O
RST
I
3
4149M–AERO–06/03
Mnemonic
Type
Name and Function
Address Latch Enable:
Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 the oscillator frequency, and can be
used for external timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory.
Program Store ENable:
The read strobe to external program memory.
When executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
External Access Enable:
EA must be externally held low to enable the
device to fetch code from external program memory locations.
Crystal 1:
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier
ALE
O (I)
PSEN
O
EA
XTAL1
XTAL2
I
I
O
4
80C32E
4149M–AERO–06/03
80C32E
Idle and Power-down
Operation
Idle mode allows the interrupt, serial port and timer blocks to continue to operate while
the clock of the CPU is gated off.
Power-down mode stops the oscillator.
Table 1.
PCON Register
PCON – Power Control Register
7
SMOD
Bit
Number
7
6
5
4
6
-
Bit
Mnemonic
SMOD
-
-
-
5
-
4
-
3
GF1
2
GF0
1
PD
0
IDL
Description
Double Baud Rate bit
Set to select double baud rate in mode 1, 2 or 3.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
General-purpose Flag
Cleared by user for General-purpose usage.
Set by user for General-purpose usage.
General-purpose Flag
Cleared by user for General-purpose usage.
Set by user for General-purpose usage.
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 000X 0000
Not bit addressable
5
4149M–AERO–06/03
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