Under locked conditions VMON should be > 0.3V and <3.0V. The input frequency may
be out of range if the voltage exceeds these levels
LVCMOS
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
Case and Electrical Ground
Frequency Output
Complementary Frequency Output – Note for LVCMOS option this pad will be tied to
GND.
Lock Detect
Locked = Logic “1”
Loss of Signal = Logic “0”
Complimentary Divided-Down VCSO/VCXO Output, or Disabled
Case and Electrical Ground
6
OD
I
7
8
9
10
GND
FOUT
CFOUT
LD
GND
O
O
O
Supply
LCPECL. LVDS or
LVCMOS
LVPECL, LVDS or
LVCMOS
LVCMOS
11
12
GND
GND
GND
GND
Supply
Supply
13
14
*
FIN
VCC
I
VCC
LVCMOS or
LVPECL
Supply
Input Frequency – AC Coupled
Power Supply Voltage (3.3 V ±5%)
For applications requiring two to four input frequencies, Vectron will assign a unique part number and the Input Frequency versus SEL[1:0] settings will be pro-
vided in a Specification Control Drawing. For single input configurations it is recommended that SEL0 and SEL1 are tied to ground.
In circuit design, when the input power is 12V or 24V, the power supply is 5V or 3.3V. We often encounter the problem of multiple power supplies.
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From Made in China 2025 to new infrastructure, to the 14th Five-Year Plan, and the country's dual carbon goals, intelligent manufacturing and industrial upgrading are all important links.
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[i=s]This post was last edited by qiushenghua on 2015-8-30 13:50[/i] Why start with 5110? It comes down to last year's low power competition, I saw many people using 5110 as the output interface. Then...
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