INTEGRATED CIRCUITS
DATA SHEET
PCF8584
I
2
C-bus controller
Product specification
Supersedes data of 1997 Mar 19
File under Integrated Circuits, IC12
1997 Oct 21
Philips Semiconductors
Product specification
I
2
C-bus controller
CONTENTS
1
2
3
4
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.8.1
6.8.1.1
6.8.1.2
6.8.1.3
6.8.1.4
6.8.1.5
6.8.1.6
6.8.2
6.8.2.1
6.8.2.2
6.8.2.3
6.8.2.4
6.8.2.5
6.8.2.6
6.8.2.7
6.9
6.10
6.11
6.11.1
6.11.2
6.12
6.12.1
6.12.2
6.12.3
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
General
Interface Mode Control (IMC)
Set-up registers S0', S2 and S3
Own address register S0'
Clock register S2
Interrupt vector S3
Data shift register/read buffer S0
Control/status register S1
Register S1 control section
PIN (Pending Interrupt Not)
ESO (Enable Serial Output)
ES1 and ES2
ENI
STA and STO
ACK
Register S1 status section
PIN bit
STS
BER
LRB/AD0
AAS
LAB
BB
Multi-master operation
Reset
Comparison to the MAB8400 I
2
C-bus interface
Deleted functions
added functions
Special function modes
Strobe
Long-distance mode
Monitor mode
7
7.1
7.2
8
9
10
11
12
13
14
14.1
15
16
16.1
16.2
16.2.1
16.2.2
16.3
16.3.1
16.3.2
16.3.3
17
18
PCF8584
SOFTWARE FLOWCHART EXAMPLES
Initialization
Implementation
I
2
C-BUS TIMING DIAGRAMS
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
I
2
C-BUS TIMING SPECIFICATIONS
PARALLEL INTERFACE TIMING
APPLICATION INFORMATION
Application Notes
PACKAGE OUTLINES
SOLDERING
Introduction
DIP
Soldering by dipping or by wave
Repairing soldered joints
SO
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
19 PURCHASE OF PHILIPS I
2
C COMPONENTS
1997 Oct 21
2
Philips Semiconductors
Product specification
I
2
C-bus controller
1
FEATURES
2
GENERAL DESCRIPTION
PCF8584
•
Parallel-bus to I
2
C-bus protocol converter and interface
•
Compatible with most parallel-bus
microcontrollers/microprocessors including 8049, 8051,
6800, 68000 and Z80
•
Both master and slave functions
•
Automatic detection and adaption to bus interface type
•
Programmable interrupt vector
•
Multi-master capability
•
I
2
C-bus monitor mode
•
Long-distance mode (4-wire)
•
Operating supply voltage 4.5 to 5.5 V
•
Operating temperature range:
−40
to +85
°C.
3
ORDERING INFORMATION
TYPE
NUMBER
PCF8584P
PCF8584T
The PCF8584 is an integrated circuit designed in CMOS
technology which serves as an interface between most
standard parallel-bus microcontrollers/microprocessors
and the serial I
2
C-bus. The PCF8584 provides both master
and slave functions.
Communication with the I
2
C-bus is carried out on a
byte-wise basis using interrupt or polled handshake.
It controls all the I
2
C-bus specific sequences, protocol,
arbitration and timing. The PCF8584 allows parallel-bus
systems to communicate bidirectionally with the I
2
C-bus.
PACKAGE
NAME
DIP20
SO20
DESCRIPTION
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads; body width 7.5 mm
VERSION
SOT146-1
SOT163-1
1997 Oct 21
3
Philips Semiconductors
Product specification
I
2
C-bus controller
4
BLOCK DIAGRAM
PARALLEL BUS
DB7
15
SDA/
(3)
SDA OUT
2
DIGITAL
FILTER
MSB
READ BUFFER
read
only
DB6
14
DB5
13
DB4
12
DB3
11
DB2
9
DB1
8
DB0
7
PCF8584
handbook, full pagewidth
V DD
20
V SS
10
DATA SHIFT REGISTER S0 AND READ BUFFER
SHIFT REGISTER
8
write
only
DATA CONTROL
COMPARATOR S0, S0'
8
MSB
(1)
X
(1)
LSB
X
OWN ADDRESS S0'
8
PCF8584
INTERRUPT VECTOR S3
SCL/
(3)
SCL IN
3
DIGITAL
FILTER
0
8
S23
default: 00H 80XX
0FH 68XXX
CLOCK REGISTER S2
0
0
S24
S22
S21
S20
CLOCK REGISTER S2
8
REGISTER S1
ENI
STA
STO
ACK
write only
read only
CONTROL STATUS
SCL CONTROL
PIN
ES0
ES1
ES2
CONTROL STATUS REGISTER S1
PIN
0
STS
BER
AD0/
LRB
AAS
LAB
BB
CLOCK PRESCALER
SCL MULTIPLEXER
BUS BUSY LOGIC
ARBITRATION LOGIC
19
RESET/
STROBE
(O.C.)
17
CS
6
A0
PARALLEL BUS CONTROL
REGISTER ACCESS CONTROL
BUS BUFFER CONTROL
INTERRUPT CONTROL
RESET/STROBE CONTROL
5
(2)
18
WR (R/W)
(2)
16
RD (DTACK)
4
1
INT
(3)
SCL OUT
IACK
CLK
(3)
SDA IN
MBD908 - 1
(1) X = don’t care.
(2) Pin mnemonics between parenthesis indicate the 68000 mode pin designations.
(3) These pin mnemonics represent the long-distance mode pin designations.
Fig.1 Block diagram.
1997 Oct 21
4
Philips Semiconductors
Product specification
I
2
C-bus controller
5
PINNING
SYMBOL
CLK
SDA or
SDA OUT
SCL or SCL IN
IACK or
SDA IN
INT or
SCL OUT
A0
PIN
1
2
3
4
I/O
I
I/O
I/O
I
DESCRIPTION
clock input from microcontroller clock generator (internal pull-up)
PCF8584
I
2
C-bus serial data input/output (open-drain). Serial data output in long-distance
mode.
I
2
C-serial clock input/output (open-drain). Serial clock input in long-distance mode.
Interrupt acknowledge input (internal pull-up); when this signal is asserted the
interrupt vector in register S3 will be available at the bus Port if the ENI flag is set.
Serial data input in long-distance mode.
Interrupt output (open-drain); this signal is enabled by the ENI flag in register S1.
It is asserted when the PIN flag is reset. (PIN is reset after 1 byte is transmitted or
received over the I
2
C-bus). Serial clock output in long-distance mode.
Register select input (internal pull-up); this input selects between the control/status
register and the other registers. Logic 1 selects register S1, logic 0 selects one of
the other registers depending on bits loaded in ESO, ES1 and ES2 of register S1.
bidirectional 8-bit bus Port 0
bidirectional 8-bit bus Port 1
bidirectional 8-bit bus Port 2
ground
bidirectional 8-bit bus Port 3
bidirectional 8-bit bus Port 4
bidirectional 8-bit bus Port 5
bidirectional 8-bit bus Port 6
bidirectional 8-bit bus Port 7
RD is the read control input for MAB8049, MAB8051 or Z80-types. DTACK is the
data transfer control output for 68000-types (open-drain).
chip select input (internal pull-up)
WR is the write control input for MAB8048, MAB8051, or Z80-types
(internal pull-up). R/W control input for 68000-types.
Reset input (open-drain); this input forces the I
2
C-bus controller into a predefined
state; all flags are reset, except PIN, which is set. Also functions as strobe output.
supply voltage
5
O
6
I
DB0
DB1
DB2
V
SS
DB3
DB4
DB5
DB6
DB7
RD (DTACK)
CS
WR (R/W)
RESET/
STROBE
V
DD
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O
I/O
I/O
−
I/O
I/O
I/O
I/O
I/O
I/(O)
I
I
I/O
−
1997 Oct 21
5
FPGA/CPLD
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