IDT72T51268L5BB datasheet, PDF

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IDT72T51268L5BB: DescriptionFIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324; Categorystorage storage; File Size521KB，56 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72T51268L5BB Overview

FIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324

IDT72T51268L5BB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
Contacts	324
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	3.6 ns
Maximum clock frequency (fCLK)	200 MHz
period time	5 ns
JESD-30 code	S-PBGA-B324
JESD-609 code	e0
length	19 mm
memory density	5242880 bit
Memory IC Type	OTHER FIFO
memory width	40
Humidity sensitivity level	3
Number of functions	1
Number of terminals	324
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX40
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA324,18X18,40
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	1.5/2.5,2.5 V
Certification status	Not Qualified
Maximum seat height	1.97 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	19 mm
Base Number Matches	1

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2.5V MULTI-QUEUE DDR FLOW-CONTROL DEVICES

40 BITS WIDE WITH FIXED 4 QUEUES

8,192 x 40 x 4, 16,384 x 40 x 4

and 32,768 x 40 x 4

IDT72T51248

IDT72T51258

IDT72T51268

FEATURES

•

The multi-queue DDR flow-control device contains 4 Queues

each queue has a fixed size of:

IDT72T51248 — 8,192 x 40 or 16,384 x 20 or 32,768 x 10

IDT72T51258 — 16,384 x 40 or 32,768 x 20 or 65,536 x 10

IDT72T51268 — 32,768 x 40 or 65,536 x 20 or 131,072 x 10

Write to and Read from the same queue or different queues

simultaneously via totally independent ports

Up to 200MHz operation of clocks

Double Data Rate, DDR is selectable, providing up to 400Mbps

bandwidth per data pin

User selectable Single or Double Data Rate modes on both the

write port and read port

100% Bus Utilization, Read and Write on every clock cycle

Global Bus Matching - All Queues have same Input bus width

and same Output bus width

User Selectable Bus Matching options:

- x40in to x40out

- x40in to x20out

- x40in to x10out

- x20in to x40out

- x20in to x20out

- x20in to x10out

- x10in to x40out

- x10in to x20out

- x10in to x10out

All I/O is LVTTL/ HSTL/ eHSTL user selectable

3.3V tolerant inputs in LVTTL mode

•

ERCLK &

EREN

Echo outputs on read port

Write Chip Select

WCS

input for write port

Read Chip Select

RCS

input for read port

User Selectable IDT Standard mode (using

and

FF)

or FWFT

mode (using

and

OR)

All 4 Queues have dedicated flag outputs

FF/IR, EF/OR, PAF

and

PAE

A Composite Full/ Input Ready Flag gives status of the queue

selected on the write port

A Composite Empty/ Output Ready flag gives status of the

queue selected on the read port

Programmable Almost Empty and Almost Full flags per Queue

Dedicated Serial Port for flag programming

A Partial Reset is provided for each queue

Power Down pin minimizes power consumption

2.5V Supply Voltage

Available in a 324-pin Plastic Ball Grid Array (PBGA)

19mm x 19mm, 1mm Pitch

JTAG port provides boundary scan function and optional

programming mode

Low Power, High Performance CMOS technology

Industrial temperature range (-40°C to +85°C)

FUNCTIONAL BLOCK DIAGRAM

MULTI-QUEUE DDR FLOW-CONTROL DEVICE

WCLK

WEN

WCS

IS[1:0]

Read Control

Write Control

8,192 x 40

16,384 x40

32,768 x 40

Queue 0

8,192 x 40

16,384 x40

32,768 x 40

Queue 1

8,192 x 40

16,384 x40

32,768 x 40

Queue 2

8,192 x 40

16,384 x40

32,768 x 40

Queue 3

RCLK

REN

RCS

OS[1:0]

D[39:0]

Data In

x10,x20,x40

Q[39:0]

Data Out

x10,x20,x40

FF0/IR0

PAF0

FF1/IR1

PAF1

FF2/IR2

PAF2

FF3/IR3

PAF3

CFF/CIR

EF0/OR0

PAE0

EF1/OR1

PAE1

EF2/OR2

PAE2

EF3/OR3

PAE3

CEF/COR

Read Port

Flag Outputs

6159 drw01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

Write Port

Flag Outputs

DECEMBER 2003

DSC-6159/2



2003

IDT72T51248/72T51258/72T51268 2.5V MULTI-QUEUE DDR FLOW-CONTROL DEVICES

8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Contents:

Features ......................................................................................................................................................................................................................... 1

Description ...................................................................................................................................................................................................................... 3

Pin Configuration ............................................................................................................................................................................................................. 5

Pin Descriptions ............................................................................................................................................................................................................ 6-8

Device Characteristics ..................................................................................................................................................................................................... 9

DC Electrical Characteristics .......................................................................................................................................................................................... 10

AC Electrical Characteristics ........................................................................................................................................................................................... 11

AC Test Conditions ........................................................................................................................................................................................................ 12

Functional Descriptions ............................................................................................................................................................................................. 14-22

Signal Descriptions ................................................................................................................................................................................................... 23-28

JTAG Timing Specifications ....................................................................................................................................................................................... 29-33

Tables:

Table 1 — Device Configuration .................................................................................................................................................................................... 14

Table 2 — Default Programmable Flag Offsets ................................................................................................................................................................ 14

Table 3 — Status Flags for IDT Standard mode ............................................................................................................................................................. 16

Table 4 — Status Flags for FWFT Mode ........................................................................................................................................................................ 16

Table 5 — I/O Voltage Level Configuration ..................................................................................................................................................................... 17

Table 6 — TSKEW Measurement .................................................................................................................................................................................. 27

Figures:

Figure 1. Multi-Queue DDR Flow-Control Device Block Diagram ..................................................................................................................................... 4

Figure 2a. AC Test Load ................................................................................................................................................................................................ 12

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 12

Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 15

Figure 4. Offset Registers Serial Bit Sequence ................................................................................................................................................................ 15

Figure 5. Bus-Matching Byte Arrangement ................................................................................................................................................................ 19-21

Figure 6. Echo Read Clock and Data Output Relationship .............................................................................................................................................. 28

Figure 7. Standard JTAG Timing ................................................................................................................................................................................... 29

Figure 8. JTAG Architecture ........................................................................................................................................................................................... 30

Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 31

Figure 10. Master Reset Timing ..................................................................................................................................................................................... 34

Figure 11. Partial Reset Timing ...................................................................................................................................................................................... 35

Figure 12. Write Cycle and Full Flag Timing (IDT Standard mode, SDR to SDR, x40 In to x40 Out) ............................................................................... 36

Figure 13. Write Cycle and Full Flag Timing in DDR mode ( IDT Standard mode, DDR to DDR, x40 In to x40 Out) ....................................................... 37

Figure 14. Write Cycle and Full Flag Timing with bus-matching and rate matching (IDT Standard mode, DDR to SDR, x10 In to x20 Out) ...................... 38

Figure 15. Write Cycle and Full Flag Timing with rate matching (IDT Standard mode, SDR to DDR, x40 In to x40 Out) .................................................. 39

Figure 16. Write Timing in FWFT mode (FWFT mode, SDR to SDR, x40 In to x40 Out) ................................................................................................. 40

Figure 17. Write Cycle and First Word Latency Timing in DDR mode (FWFT mode, DDR to DDR, x40 In to x40 Out) .................................................... 41

Figure 18. Read Cycle, Empty Flag & First Word Latency (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .......................................................... 42

Figure 19. Read Cycle, Empty Flag & First Word Latency in DDR mode (IDT Standard mode, DDR to DDR, x40 In to x40 Out) ................................... 43

Figure 20. Read Cycle, Empty Flag & First Word Latency with bus-matching and rate-matching (IDT Standard mode, DDR to SDR, x40 In to x20 Out) . 44

Figure 21. Read Cycle and Empty Flag Timing with bus-matching and rate-matching (IDT Standard mode, SDR to DDR, x10 In to x20 Out) ................. 45

Figure 22. Read Timing at Full Boundary (FWFT mode, SDR to SDR, x40 In to x40 Out) ............................................................................................. 46

Figure 23. Composite Empty Flag (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .............................................................................................. 47

Figure 24. Composite Output Ready Flag (FWFT mode, SDR to SDR, x40 In to x40 Out) ............................................................................................. 47

Figure 25. Composite Full Flag (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .................................................................................................. 48

Figure 26. Composite Input Ready Flag (FWFT mode, SDR to SDR, x40 In to x40 Out) ................................................................................................ 48

Figure 27. Queue Switch at Every Clock Cycle (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .......................................................................... 49

Figure 28. Echo Read Clock and Read Enable Operation (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .......................................................... 50

Figure 29. Echo RCLK and Echo Read Enable Operation (FWFT mode, SDR to SDR, x40 In to x40 Out) .................................................................... 51

Figure 30. Echo Read Clock and Read Enable Operation (IDT Standard mode, DDR to DDR, x10 In to x10 Out) ......................................................... 52

Figure 31. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 53

Figure 32. Reading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 53

Figure 34. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT mode, SDR to SDR, x40 In to x40 Out) ........................... 54

Figure 33. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT mode, SDR to SDR, x40 In to x40 Out) .............................. 54

Figure 35. Power Down Operation ................................................................................................................................................................................ 55

IDT72T51268L5BB Related Products

	IDT72T51268L5BB	IDT72T51248L5BBI	IDT72T51268L5BBI	IDT72T51258L5BBI	IDT72T51268L6-7BBI	IDT72T51268L6-7BB
Description	FIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	FIFO, 32KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	FIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	FIFO, 64KX40, 3.6ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
Contacts	324	324	324	324	324	324
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	3.6 ns	3.6 ns	3.6 ns	3.6 ns	3.8 ns	3.8 ns
Maximum clock frequency (fCLK)	200 MHz	200 MHz	200 MHz	200 MHz	150 MHz	150 MHz
period time	5 ns	5 ns	5 ns	5 ns	6.7 ns	6.7 ns
JESD-30 code	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324	S-PBGA-B324
JESD-609 code	e0	e0	e0	e0	e0	e0
length	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm
memory density	5242880 bit	1310720 bit	5242880 bit	2621440 bit	5242880 bit	5242880 bit
Memory IC Type	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
memory width	40	40	40	40	40	40
Humidity sensitivity level	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1
Number of terminals	324	324	324	324	324	324
word count	131072 words	32768 words	131072 words	65536 words	131072 words	131072 words
character code	128000	32000	128000	64000	128000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	85 °C	85 °C	85 °C	85 °C	70 °C
Minimum operating temperature	-	-40 °C	-40 °C	-40 °C	-40 °C	-
organize	128KX40	32KX40	128KX40	64KX40	128KX40	128KX40
Exportable	YES	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40	BGA324,18X18,40
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	225	225	225	225	225	225
power supply	1.5/2.5,2.5 V	1.5/2.5,2.5 V	1.5/2.5,2.5 V	1.5/2.5,2.5 V	1.5/2.5,2.5 V	1.5/2.5,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.97 mm	1.97 mm	1.97 mm	1.97 mm	1.97 mm	1.97 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	20	20	20	30	30
width	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm
Base Number Matches	1	1	1	1	1	1
Maker	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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