IDT71V3577S85PFG datasheet, PDF

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IDT71V3577S85PFG: Description128K X 36 CACHE SRAM, 7.5 ns, PQFP100; Categorystorage; File Size292KB，22 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT71V3577S85PFG Overview

128K X 36 CACHE SRAM, 7.5 ns, PQFP100

IDT71V3577S85PFG Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
Rated supply voltage	3.3 V
Minimum supply/operating voltage	3.14 V
Maximum supply/operating voltage	3.46 V
Processing package description	14 X 20 MM, PLASTIC, TQFP-100
each_compli	Yes
EU RoHS regulations	Yes
state	Active
ccess_time_max	7.5 ns
jesd_30_code	R-PQFP-G100
jesd_609_code	e3
storage density	4.72E6 bi
Memory IC type	CACHE SRAM
memory width	36
moisture_sensitivity_level	3
Number of digits	131072 words
Number of digits	128K
operating mode	SYNCHRONOUS
organize	128KX36
Packaging Materials	PLASTIC/EPOXY
ckage_code	LQFP
packaging shape	RECTANGULAR
Package Size	FLATPACK, LOW PROFILE
serial parallel	PARALLEL
eak_reflow_temperature__cel_	260
qualification_status	COMMERCIAL
seated_height_max	1.6 mm
surface mount	YES
Craftsmanship	CMOS
Temperature level	COMMERCIAL
terminal coating	MATTE TIN
Terminal form	GULL WING
Terminal spacing	0.6500 mm
Terminal location	QUAD
ime_peak_reflow_temperature_max__s_	30
length	20 mm
width	14 mm
dditional_feature	FLOW-THROUGH ARCHITECTURE

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128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Features

IDT71V3577S

IDT71V3579S

IDT71V3577SA

IDT71V3579SA

Description

The IDT71V3577/79 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to gen-

erate a self-timed write based upon a decision which can be left until the

end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V3577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5280 tbl 01

128K x 36, 256K x 18 memory configurations

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW byte write

GW),

enable (BWE and byte writes (BW

BWE),

BWx)

BWE

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Pin Description Summary

-A

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

NOTE:

and

are not applicable for the IDT71V3579.

FEBRUARY 2005

DSC-5280/08

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