Freescale Semiconductor
Advance Information
Document Number: MC33926
Rev. 9.0, 12/2009
5.0 A Throttle Control H-Bridge
The 33926 is a monolithic H-Bridge Power IC designed primarily
for automotive electronic throttle control, but is applicable to any low-
voltage DC servo motor control application within the current and
voltage limits stated in this specification.
The 33926 is able to control inductive loads with currents up to
5.0 A peak. RMS current capability is subject to the degree of
heatsinking provided to the device package. Internal peak-current
limiting (regulation) is activated at load currents above 6.5 A ± 1.5 A.
Output loads can be pulse width modulated (PWM’ed) at frequencies
up to 20 kHz. A load current feedback feature provides a proportional
(0.24% of the load current) current output suitable for monitoring by a
microcontroller’s A/D input. A Status Flag output reports under-
voltage, over-current, and over-temperature fault conditions.
Two independent inputs provide polarity control of two half-bridge
totem-pole outputs. Two independent disable inputs are provided to
force the H-Bridge outputs to tri-state (high-impedance off-state). An
inverted input changes the IN1 and IN2 inputs to LOW = true logic.
Features
33926
AUTOMOTIVE THROTTLE H-BRIDGE
ACTUATOR/ MOTOR EXCITER
Bottom View
SCALE 2:1
PNB SUFFIX (Pb-FREE)
98ARL10579D
32-PIN PQFN
• 5.0 to 28 V continuous operation (transient operation from 5.0 to
40 V)
• 225 mΩ maximum R
DS(ON)
@ 150°C (each H-Bridge MOSFET)
ORDERING INFORMATION
• 3.0 V and 5.0 V TTL / CMOS logic compatible inputs
Temperature
Device
Package
• Over-current limiting (Regulation) via an internal constant-off-time
Range (T
A
)
PWM
MC33926PNB/R2 -40°C to 125°C
32 PQFN
• Output short-circuit protection (short to VPWR or ground)
• Temperature-dependent current-limit threshold reduction
• All Inputs have an internal source/sink to define the default (floating input) states
• Sleep mode with current draw < 50 µA (with inputs floating or set to match default logic states)
• Pb-free packaging designated by suffix code PNB
V
DD
V
PWR
33926
SF
FB
IN1
IN2
VPWR
CCP
OUT1
MOTOR
OUT2
PGND
AGND
MCU
INV
SLEW
D1
D2
EN
Figure 1. 33926 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
LOGIC SUPPLY
VDD
CCP
VCP CHARGE
PUMP
TO GATES
HS1
HS2
OUT1
OUT2
EN
IN1
IN2
D2
D1
INV
SLEW
SF
FB
AGND
GATE DRIVE
AND
PROTECTION
LOGIC
HS1
LS1
HS2
LS2
VSENSE
ILIM PWM
LS1
LS2
PGND
CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
PGND
Figure 2. 33926 Simplified Internal Block Diagram
33926
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VPWR
OUT2
OUT2
OUT2
OUT2
CCP
IN2
IN1
SLEW
1
2
3
4
5
6
7
8
9
32 31 30 29 28 27 26
D1
25
24
23
22
NC
PGND
PGND
PGND
SF
PGND
PGND
PGND
NC
Transparent Top
View of Package
VPWR
AGND
VPWR
INV
FB
NC
AGND
21
20
19
18
10 11 12 13 14 15 16
OUT1
OUT1
OUT1
VPWR
OUT1
EN
D2
17
Figure 3. 33926 Pin Connections
Table 1. 33926 Pin Definitions
A functional description of each pin can be found in the Functional Description section beginning on
page 12.
Pin
1
Pin Name
IN2
Pin
Function
Logic Input
Formal Name
Input 2
Definition
Logic input control of OUT2; e.g., when IN2 is logic HIGH, OUT2 is set to V
PWR
,
and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger input with
~ 80
μA
source so default condition = OUT2 HIGH.)
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to V
PWR
,
and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with
~ 80
μA
source so default condition = OUT1 HIGH.)
Logic input to select fast or slow slew rate. (Schmitt trigger input with ~ 80
μA
sink so default condition = slow.)
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the PCB.
The low current analog signal ground must be connected to PGND via low
impedance path (<<10 mΩ, 0 Hz to 20 kHz). Exposed copper pad is also the
main heatsinking path for the device.
Sets IN1 and IN2 to logic LOW = TRUE. (Schmitt trigger input with ~ 80
μA
sink
so default condition = non-inverted.)
Load current feedback output provides ground referenced 0.24% of H-Bridge
high-side output current. (Tie pin to GND through a resistor if not used.)
No internal connection is made to this pin.
When EN is logic HIGH, the device is operational. When EN is logic LOW, the
device is placed in Sleep mode. (logic input with ~ 80
μA
sink so default
condition = Sleep mode.)
2
IN1
Logic Input
Input 1
3
4, 6, 11, 31
5,
Exposed
Pad
7
8
9, 17, 25
10
SLEW
VPWR
AGND
Logic Input
Power Input
Analog
Ground
Logic Input
Analog
Output
Slew Rate
Positive Power
Supply
Analog Signal
Ground
Input Invert
Feedback
No Connect
INV
FB
NC
EN
Logic Input
Enable Input
33926
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33926 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Description section beginning on
page 12.
Pin
12, 13,
14, 15
16
18 – 20,
22 – 24
21
Pin Name
OUT1
D2
PGND
Pin
Function
Power
Output
Logic Input
Power
Ground
Logic
Output -
Open Drain
Logic Input
Power
Output
Analog
Output
Formal Name
H-Bridge Output 1
Disable Input 2
(Active Low)
Power Ground
Definition
Source of high-side MOSFET1 and drain of low-side MOSFET1.
When
D2
is logic LOW, both OUT1 and OUT2 are tri-stated. (Schmitt trigger
input with ~80
μA
sink so default condition = disabled.)
High-current power ground pins must be connected together physically as
close as possible and directly soldered down to a wide, thick, low resistance
ground plane on the PCB.
Open drain active LOW status flag output (requires an external pull-up resistor
to V
DD
. Maximum permissible load current < 0.5 mA. Maximum V
CEsat
< 0.4 V
@
0.3 mA. Maximum permissible pullup voltage < 7.0 V.)
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger
input with ~80
μA
source so default condition = disabled.
Source of high-side MOSFET2 and drain of low-side MOSFET2.
External reservoir capacitor connection for internal charge pump; connected to
VPWR. Allowable values are 30 to 100
ηF.
Note: This capacitor is required for
the proper performance of the device.
SF
Status Flag
(Active Low)
Disable Input 1
(Active High)
H-Bridge Output 2
Charge Pump
Capacitor
26
27, 28,
29, 30
32
D1
OUT2
CCP
33926
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device. These parameters are not production tested.
Ratings
ELECTRICAL RATINGS
Power Supply Voltage
Normal Operation (Steady-state)
Transient Over-voltage
Logic Input Voltage
(2)
SF Output
(3)
Continuous Output Current
(4)
ESD Voltage
(5)
Human Body Model
Machine Model
Charge Device Model
Corner Pins (1,9,17,25)
All Other Pins
THERMAL RATINGS
Storage Temperature
Operating Temperature
(6)
Ambient
Junction
T
A
T
J
-
40 to 125
-
40 to 150
T
STG
-
65 to 150
V
ESD2
±750
±500
V
ESD1
± 2000
± 200
(1)
Symbol
Value
Unit
V
V
PWR(SS)
V
PWR(t)
V
IN
V
SF
I
OUT(CONT)
- 0.3 to 28
- 0.3 to 40
- 0.3 to 7.0
- 0.3 to 7.0
5.0
V
V
A
V
°
C
°
C
Notes
1. Device will survive repetitive transient overvoltage conditions for durations not to exceed 500 ms
@
duty cycle not to exceed 10%.
External protection is required to prevent device damage in case of a reverse battery condition.
2. Exceeding the maximum input voltage on IN1, IN2, EN, INV, SLEW, D1, or D2 may cause a malfunction or permanent damage to the
device.
3. Exceeding the pullup resistor voltage on the open drain
SF
pin may cause permanent damage to the device.
4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature
≤
150
°
C.
5. ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω),
ESD2 testing is performed in
accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω),
and the Charge Device Model (CDM), Robotic (C
ZAP
= 4.0pF).
6.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
non-repetitive excursions of junction temperature above 150
°
C can be tolerated provided the duration does not exceed 30 seconds
maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.)
33926
Analog Integrated Circuit Device Data
Freescale Semiconductor
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